James H. Scheuneman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
Abstract: An improvement to a semiconductor memory subsystem containing single bit error correction/double bit error detection (SBC/DBD) which provides correction of double bit errors through the utilization of a modest amount of additional circuitry. The present invention accomplishes this result through the technique of sequentially complementing each double bit pair within the semiconductor memory subsystem data word determined to contain a multiple error and rechecking the modified data word with the existing SBC/DBD circuitry, one double bit pair at a time, until it is determined by the SBC/DBD circuitry that such double bit pair complementing has corrected the double bit error.
Abstract: A method of and an apparatus for obtaining double bit error correction capabilities in a large scale integrated (LSI) semiconductor memory system using only single bit error correction, double bit error detection (SEC, DED) logic are disclosed. The method is based upon the statistical assumption that in a large scale integrated semiconductor memory, substantially all errors in the data bits that make up a data word are initially a single bit error and that increasing multiple, i.e., double, triple, etc., bit errors occur in a direct increasing ratio of the use or selection of the data word. In the present invention, all data words are priorly tested to be error free. Subsequent detection of single bit errors results in the correction of the single bit error and the storage of the single bit error correcting syndrome bits in a syndrome bit memory.