Patents by Inventor James Harold Atherton
James Harold Atherton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9805227Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: GrantFiled: July 23, 2015Date of Patent: October 31, 2017Assignee: Ruizhang Technology Limited CompanyInventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Patent number: 9218519Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: GrantFiled: March 8, 2013Date of Patent: December 22, 2015Assignee: Alien Technology CorporationInventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20150332138Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: July 23, 2015Publication date: November 19, 2015Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20150169908Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: September 12, 2014Publication date: June 18, 2015Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20130300540Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: March 8, 2013Publication date: November 14, 2013Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Patent number: 8395505Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: GrantFiled: April 7, 2009Date of Patent: March 12, 2013Assignee: Alien Technology CorporationInventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Publication number: 20120249303Abstract: Methods and apparatuses for selecting a subset of RFID tags are provided in some embodiments. These methods and apparatuses utilize the susceptibility to light by persistent nodes found in passive tags. Light can be used to intentionally reduce persistence times in a particular subset tags or even an individual tag. Then, persistent nodes can be used as a selection criterion to distinguish previously illuminated tags from non-illuminated tags. In other embodiments, a power circuit receives a RF input source and generates a direct current (DC) output voltage. The circuit includes a bias circuit to supply a gate to source bias, which is independent of the DC output voltage. The circuit further includes a voltage multiplier circuit that is coupled to the bias circuit. The voltage multiplier circuit has MOS transistors with one transistor to receive the gate to source bias.Type: ApplicationFiled: April 7, 2009Publication date: October 4, 2012Inventors: Mark Alfred Hadley, James Harold Atherton, Jay Tu, Edward John Boling, John Stephen Smith
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Patent number: 7864136Abstract: A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The tiles are formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile.Type: GrantFiled: August 30, 2006Date of Patent: January 4, 2011Inventors: Dennis Lee Matthies, Roger Green Stewart, James Harold Atherton, Dennis J. Hechis, Heinz H. Busta, Zilan Shen
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Patent number: 7592970Abstract: A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The tiles are formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile.Type: GrantFiled: October 1, 2004Date of Patent: September 22, 2009Inventors: Dennis Lee Matthies, Roger Green Stewart, James Harold Atherton, Dennis J. Bechis, Heinz H. Busta, Zilan Shen
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Publication number: 20080174515Abstract: A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The tiles are formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode. The connecting pads on the display section are electrically connected and physically joined to corresponding connecting pads on the electronics section to form a complete tile.Type: ApplicationFiled: August 30, 2006Publication date: July 24, 2008Inventors: Dennis Lee Matthies, Roger Green Stewart, James Harold Atherton, Dennis J. Hechis, Heinz H. Busta, Zilan Shen
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Patent number: 6897855Abstract: A tiled display device is formed from display tiles having picture element (pixel) positions defined up to the edge of the tiles. Each pixel position has an organic light-emitting diode (OLED) active area which occupies approximately 25 percent of the pixel area. Each tile includes a memory which stores display data, and pixel driving circuitry which controls the scanning and illumination of the pixels on the tile. The pixel driving circuitry is located on the back side of the tile and connections to pixel electrodes on the front side of the tile are made by vias which pass through portions of selected ones of the pixel areas which are not occupied by the active pixel material. The tiles are to formed in two parts, an electronics section and a display section. Each of these parts includes connecting pads which cover several pixel positions. Each connecting pad makes an electrical connection to only one row electrode or column electrode.Type: GrantFiled: February 16, 1999Date of Patent: May 24, 2005Assignee: Sarnoff CorporationInventors: Dennis Lee Matthies, Roger Green Stewart, James Harold Atherton, Dennis J. Bechis, Heinz H. Busta, Zilan Shen
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Patent number: 6618030Abstract: LED pixel structures and methods that improve brightness uniformity by reducing current nonuniformities in a light-emitting diode of the pixel structures are disclosed.Type: GrantFiled: February 27, 2001Date of Patent: September 9, 2003Assignees: Sarnoff Corporation, Mitsubishi Chemical CorporationInventors: Michael Gillis Kane, James Harold Atherton, Roger Green Stewart, Frank Paul Cuomo
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Patent number: 6507327Abstract: A three electrode plasma display panel (PDP) operates in concurrent sustain and addressing periods, rather than separating the sustain and addressing periods. Because of this concurrent operation, a PDP with a brighter display is produced. Crosstalk between sustain electrodes and the column electrodes of non-selected rows is mitigated by implementing column voltages such that there is no difference in crosstalk brightness levels in non-addressed pixels in the on state compared to non-addressed pixels in the off state. This is accomplished by choosing column voltages that are approximately symmetric about one-half of the sustain voltage.Type: GrantFiled: January 21, 2000Date of Patent: January 14, 2003Assignee: Sarnoff CorporationInventors: James Harold Atherton, Michael Gillis Kane
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Patent number: 6476783Abstract: A display device having features which enhance the contrast of displayed images includes a pixel structure that defines an active pixel area and an inactive pixel area. The display device may be an emissive device such as an OLED or electroluminescent device, a transmissive device such as a liquid crystal light-valve device or a reflective device, such as a Bistable, Reflective Cholesteric (BRC) liquid crystal device. The ratio of the active pixel area to the total pixel area is less than 50 percent. The display device includes a transparent cover plate having a black matrix formed on the viewer side of the cover plate. The display device may be a tiled display in which case the black matrix is formed on an integrator plate to which the individual tiles are bound to form the complete display device. For reflective or emissive display materials, the display device includes an electronics section including a circuit board which provides driving signals for the pixels of the display device.Type: GrantFiled: February 16, 1999Date of Patent: November 5, 2002Assignee: Sarnoff CorporationInventors: Dennis Lee Matthies, Zilan Shen, Roger Green Stewart, James Harold Atherton
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Patent number: 6466194Abstract: A display device includes a column driver having an initialization sequence in the vertical blanking interval. The signal used to render the column driver TFT conductive is determined in the vertical blanking interval and maintained on a capacitor in the column driver for the duration of the vertical field. The column driver also includes an autozero comparator which is subject to the autozero operation during the vertical blanking interval.Type: GrantFiled: December 29, 1999Date of Patent: October 15, 2002Assignee: Sarnoff CorporationInventor: James Harold Atherton
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Publication number: 20020050958Abstract: A display device having features which enhance the contrast of displayed images includes a pixel structure that defines an active pixel area and an inactive pixel area. The display device may be an emissive device such as an OLED or electroluminescent device, a transmissive device such as a liquid crystal light-valve device or a reflective device, such as a Bistable, Reflective Cholesteric (BRC) liquid crystal device. The ratio of the active pixel area to the total pixel area is less than 50 percent. The display device includes a transparent cover plate having a black matrix formed on the viewer side of the cover plate. The display device may be a tiled display in which case the black matrix is formed on an integrator plate to which the individual tiles are bound to form the complete display device. For reflective or emissive display materials, the display device includes an electronics section including a circuit board which provides driving signals for the pixels of the display device.Type: ApplicationFiled: February 16, 1999Publication date: May 2, 2002Inventors: DENNIS LEE MATTHIES, ZILAN SHEN, ROGER GREEN STEWART, JAMES HAROLD ATHERTON
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Patent number: 6370019Abstract: A plurality of sealing methods may be used either alone or in combination with each other to seal an electronic display structure. The display module includes a first substrate having a plurality of column electrodes. Each of a plurality of portions of a display material are coupled to one of the plurality of column electrodes and to one of a plurality of row electrodes. A pixel seal may be formed over the display material to encapsulate the display material. An area seal may be formed upon the first substrate to encapsulates the row electrodes, the column electrodes, and the portions of display material. A bead seal may be formed around the perimeter of the first substrate to couple it to a second substrate while sealing the internal display material. An edge seal may be formed by a banded structure spanning from the first substrate to the second substrate and extending around the perimeter of the substrates.Type: GrantFiled: February 16, 1999Date of Patent: April 9, 2002Assignee: Sarnoff CorporationInventors: Dennis Lee Matthies, Zilan Shen, Roger Green Stewart, James Harold Atherton
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Patent number: 6348906Abstract: A row-select circuit for an organic light emitting diode display propagates a gating pulse through a shift register. This gating pulse is synchronized with a system clock signal and is used to selectively apply a plurality of broadcast control signals to a selected row of pixels on the display. The line scanning circuitry is controlled to clear and autozero the pixels in the display either one line at a time or the entire image frame at a time. According to another aspect of the invention, the clearing of a row of pixels in the display is performed over several line intervals before the row is autozeroed and loaded with new values. According to yet another aspect of the invention, the broadcast control signals may be adapted to achieve the best performance for each display device.Type: GrantFiled: August 26, 1999Date of Patent: February 19, 2002Assignee: Sarnoff CorporationInventors: Robin Mark Adrian Dawson, Zilan Shen, Alfred Charles Ipri, Roger Green Stewart, James Harold Atherton, Stephen John Connor
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Publication number: 20010024186Abstract: LED pixel structures and methods that improve brightness uniformity by reducing current nonuniformities in a light-emitting diode of the pixel structures are disclosed.Type: ApplicationFiled: February 27, 2001Publication date: September 27, 2001Applicant: SARNOFF CORPORATIONInventors: Michael Gillis Kane, James Harold Atherton, Roger Green Stewart, Frank Paul Cuomo
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Patent number: 6259838Abstract: A display as for images and/or information comprises a plurality of linearly addressed light-emitting fibers disposed in side-by-side arrangement to define a viewing surface. Each light-emitting fiber includes a plurality of light-emitting elements disposed along its length which is linearly addressed by signals provided by a drive circuit at one end thereof. Linear addressing signals are either optical signals or electrical signals, and may be frequency modulated, digitally encoded or analog encoded. A detector associated with each pixel detects the linear addressing signal and decodes same to activate and deactivate organic or inorganic light-emitting material elements. Thus, the light-emitting elements emit light to display a pixel or sub-pixel of the image and/or information. The light-emitting fiber may include a transparent fiber as substrate for propagating the optical signals therethrough and may include electrical conductors disposed along its length for propagating the electrical signals.Type: GrantFiled: October 15, 1999Date of Patent: July 10, 2001Assignee: Sarnoff CorporationInventors: Bawa Singh, William Ronald Roach, Satyam Choudary Cherukuri, Peter John Zanzucchi, Israel Kalish, James Harold Atherton