Patents by Inventor James L. Burrows

James L. Burrows has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4694411
    Abstract: A method and apparatus for simulating a network comprising a plurality of processing elements useful in simulating, for example, complex digital combinatorial electronic logic circuits. Each type of digital logic element is assigned a symbol, and the symbols are stored in an array pattern in a memory, with the row and column addresses of the symbols in memory corresponding to their position in the network. The simulator sequentially retrieves each element in the network starting from an input and determines the element response to an input signal based on the type of element and the signals input to it. After all of the elements in the network have been processed, the simulated output of the network is available at the network output elements.
    Type: Grant
    Filed: February 4, 1985
    Date of Patent: September 15, 1987
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows
  • Patent number: 4628477
    Abstract: A data stack for storing data at sequential locations in a memory and for transmitting the data in modes defined by commands from a host data processing system. A random access memory stores the data in sequential locations at addresses selected by a state signal generator comprising read only memory. The state generator generates the addresses and read/write control signals for the random access memory in response to the commands from the host system and a previous address provided by the generator.
    Type: Grant
    Filed: October 17, 1983
    Date of Patent: December 9, 1986
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows
  • Patent number: 4607176
    Abstract: A tally cell circuit for counting the number of logical ones in an input signal utilizing a parallel-series combination of four CMOS field-effect transistors. The number of input ones in the input are expressed in a binary code at the output of the tally cell circuit.
    Type: Grant
    Filed: August 22, 1984
    Date of Patent: August 19, 1986
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventors: James L. Burrows, Stephen B. Butler
  • Patent number: 4604723
    Abstract: A bit-slice adder circuit for adding a plurality of input numbers in binary form. A tally circuit receives all of the bits from a bit position of all of the numbers and identifies the number of "ones" in that bit position. This information is coupled as address signals to a memory, which also receives, as address signals, carry signals. Each storage location at each address in the memory stores the sum of the carry portion of the location's address and the "ones" portion of the address signals from the tally circuit. The least significant bit of the addressed storage location is coupled to a shift register, and the remaining bits comprise the carry signals that are coupled to the memory's address input for the next signal from the tally circuit. After all of the bit positions in the input numbers have been coupled through the tally circuit, the sum is generated which comprises the last carry signal concatenated with the bits stored in the shift register.
    Type: Grant
    Filed: October 17, 1983
    Date of Patent: August 5, 1986
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows
  • Patent number: 4600846
    Abstract: Universal logic circuit cells for use in designing and laying out electronic circuits. The cells provide AND and OR on other logical functions on input signals, and include a conventional AND or OR gate, or other logic gate, and associated input and output connections and circuitry that enables them to be used in many applications. The cells simplify laying out a combinatorial logic circuit after it has been designed.
    Type: Grant
    Filed: October 6, 1983
    Date of Patent: July 15, 1986
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows
  • Patent number: 4584664
    Abstract: Apparatus for sorting two input numbers including a memory that iteratively receives a digit from both of the numbers and transmits output signals corresponding to the input digits, the digits of the larger number being transmitted on one output line and the digits of the smaller number being transmitted onto another output line. The apparatus includes a memory that receives, as address signals, the state signal and signals corresponding to the input digits. The state signal determines the output lines onto which the next pair of input digits are to be transmitted.
    Type: Grant
    Filed: October 17, 1983
    Date of Patent: April 22, 1986
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows
  • Patent number: 4558236
    Abstract: A universal logic circuit that performs a selected one of several logic operations on a pair of input signals in response to the receipt of a control signal and the terminals to which the input signals and control signal are coupled.
    Type: Grant
    Filed: October 17, 1983
    Date of Patent: December 10, 1985
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows
  • Patent number: 4528641
    Abstract: A variable radix processor is constructed on 1.25 micrometer CMOS/SOS. The processor, based upon a predetermined algorithm, is constructed to process radix 2 to 7 data wherein the data is input in a parallel-by-word, parallel-by-bit format. A format selection switch has the data input whereafter a plurality of switches outputs an address format to a bit-slice multiply-adder. The bit slice multiply-adder has ROMs addressed by the format selection switch. Based upon the predetermined algorithm, each unique address format causes the ROMs to output a unique word in parallel bits to a tally cascade circuit and then to a fast-carry adder. The processor can operate on a transfer function such as Z.sub.A =.+-.(A.+-.C), Z.sub.B =B where A=.SIGMA.a.sub.i X.sub.i, B=b.sub.i X.sub.i with very high throughput rates such as 380 million operations per second.
    Type: Grant
    Filed: November 16, 1982
    Date of Patent: July 9, 1985
    Assignee: The United States of America as represented by the Secretary of the Air Force
    Inventor: James L. Burrows
  • Patent number: 4327407
    Abstract: A data driven processor for searching data stored in memory to identify messages or other data containing operator selected keywords containing alpha-numeric or other characters and for performing arithmetic and other functions performed by processors. The processor comprises a plurality of commercially available integrated circuit random access memories (RAMs). The binary words read out of the RAMs are applied to the higher order addressing inputs of the same RAMs. Messages being searched for keywords are applied to the lower order addressing inputs of the same RAMs. A binary word applied to the higher order addressing inputs of the RAM memory selects a block of memory bits with each bit being associated with a different character. Only the memory bit within a selected block of memory bits corresponding to the keyword character being searched for contains a binary word indicating the block of bits for the subsequent keyword character to be searched for.
    Type: Grant
    Filed: February 26, 1979
    Date of Patent: April 27, 1982
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows
  • Patent number: 4254476
    Abstract: An associative processor for searching data stored in memory to identify messages or other data containing operator selected keywords containing alpha-numeric or other characters is disclosed. The identified messages or other data are then transferred from the memory to an output device for review. The processor comprises a plurality of commercially available integrated circuit random access memories (RAMs) for performing processing functions. The binary words read out of the RAMs are applied via a register to the higher order addressing inputs of the same RAMs without any processing. Messages being searched for keywords are applied to the lower order addressing inputs of the same RAMs. A binary word applied to the higher order addressing inputs of the RAM memory selects a block of memory bits with each bit being associated with a different character.
    Type: Grant
    Filed: June 25, 1979
    Date of Patent: March 3, 1981
    Assignee: Sanders Associates, Inc.
    Inventor: James L. Burrows