Patents by Inventor James M. O'Connor

James M. O'Connor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150293845
    Abstract: Described is a system and method for a multi-level memory hierarchy. Each level is based on different attributes including, for example, power, capacity, bandwidth, reliability, and volatility. In some embodiments, the different levels of the memory hierarchy may use an on-chip stacked dynamic random access memory, (providing fast, high-bandwidth, low-energy access to data) and an off-chip non-volatile random access memory, (providing low-power, high-capacity storage), in order to provide higher-capacity, lower power, and higher-bandwidth performance. The multi-level memory may present a unified interface to a processor so that specific memory hardware and software implementation details are hidden. The multi-level memory enables the illusion of a single-level memory that satisfies multiple conflicting constraints. A comparator receives a memory address from the processor, processes the address and reads from or writes to the appropriate memory level.
    Type: Application
    Filed: April 11, 2014
    Publication date: October 15, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Lisa R. Hsu, James M. O'Connor, Vilas K. Sridharan, Gabriel H. Loh, Nuwan S. Jayasena, Bradford M. Beckmann
  • Patent number: 9135185
    Abstract: A die-stacked memory device incorporates a data translation controller at one or more logic dies of the device to provide data translation services for data to be stored at, or retrieved from, the die-stacked memory device. The data translation operations implemented by the data translation controller can include compression/decompression operations, encryption/decryption operations, format translations, wear-leveling translations, data ordering operations, and the like. Due to the tight integration of the logic dies and the memory dies, the data translation controller can perform data translation operations with higher bandwidth and lower latency and power consumption compared to operations performed by devices external to the die-stacked memory device.
    Type: Grant
    Filed: December 23, 2012
    Date of Patent: September 15, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Bradford M. Beckmann, James M. O'Connor, Michael Ignatowski, Michael J. Schulte, Lisa R. Hsu, Nuwan S. Jayasena
  • Publication number: 20150256983
    Abstract: A base station (103) assigns a set of mobile stations (101) to a group wherein the group will share a set of radio resources (770). A shared control channel information element (501) is sent to the group of mobile stations (101) and provides a bitmap having fields for group ordering (511), resource allocations (530), continuation resources (540) for HARQ, and an ordering pattern (513). If a mobile station requires retransmission it will access the resources indicated by the continuation resources field (54) in order to receive data. The HARQ blocks may be assigned to a mobile station based upon an index (601) which may correspond to the mobile station vocoder rate. Further, HARQ subgroups may be defined to associate subgroups of mobile stations with specific HARQ transmission opportunities on the super-frame and allocated by a rotating bitmap.
    Type: Application
    Filed: May 20, 2015
    Publication date: September 10, 2015
    Inventors: Jack A. Smith, Hao Bi, Sean M. Mcbeath, James M. O'connor, Danny Pinckley, John D. Reed
  • Patent number: 9106260
    Abstract: A processor system as presented herein includes a processor core, cache memory coupled to the processor core, a memory controller coupled to the cache memory, and a system memory component coupled to the memory controller. The system memory component includes a plurality of independent memory channels configured to store data blocks, wherein the memory controller controls the storing of parity bits in at least one of the plurality of independent memory channels. In some implementations, the system memory is realized as a die-stacked memory component.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: August 11, 2015
    Assignee: ADVANCED MICRO DEVICES, INC.
    Inventors: James M. O'Connor, Vilas K. Sridharan, Gabriel H. Loh
  • Publication number: 20150205296
    Abstract: A facility for automated modelling of the cutting process for a particular material to be cut by a beam cutting tool, such as a waterjet cutting system, from empirical data to predict aspects of the waterjet's effect on the workpiece across a range of material thicknesses, across a range of cutting geometries, and across a range of cutting quality levels, all of which may be broader than, and independent of the actual requirements for a target workpiece, is described.
    Type: Application
    Filed: January 21, 2015
    Publication date: July 23, 2015
    Inventors: Axel H. Henning, James M. O'Connor
  • Publication number: 20150199126
    Abstract: A die-stacked hybrid memory device implements a first set of one or more memory dies implementing first memory cell circuitry of a first memory architecture type and a second set of one or more memory dies implementing second memory cell circuitry of a second memory architecture type different than the first memory architecture type. The die-stacked hybrid memory device further includes a set of one or more logic dies electrically coupled to the first and second sets of one or more memory dies, the set of one or more logic dies comprising a memory interface and a page migration manager, the memory interface coupleable to a device external to the die-stacked hybrid memory device, and the page migration manager to transfer memory pages between the first set of one or more memory dies and the second set of one or more memory dies.
    Type: Application
    Filed: January 10, 2014
    Publication date: July 16, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Nuwan S. Jayasena, Gabriel H. Loh, James M. O'Connor, Niladrish Chatterjee
  • Patent number: 9075730
    Abstract: A system and method for efficiently limiting storage space for data with particular properties in a cache memory. A computing system includes a cache and one or more sources for memory requests. In response to receiving a request to allocate data of a first type, a cache controller allocates the data in the cache responsive to determining a limit of an amount of data of the first type permitted in the cache is not reached. The controller maintains an amount and location information of the data of the first type stored in the cache. Additionally, the cache may be partitioned with each partition designated for storing data of a given type. Allocation of data of the first type is dependent at least upon the availability of a first partition and a limit of an amount of data of the first type in a second partition.
    Type: Grant
    Filed: December 21, 2012
    Date of Patent: July 7, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Mithuna S. Thottethodi, Gabriel H. Loh, James M. O'Connor, Yasuko Eckert, Bradford M. Beckmann
  • Publication number: 20150174732
    Abstract: A waterjet system in accordance with a particular embodiment includes a pressurizing device configured to pressurize a fluid, a cutting head downstream from the pressurizing device, and a catcher positioned to collect a jet from the cutting head. The system can further include a treatment assembly configured to treat a feed fluid to the pressurizing device and/or a byproduct fluid from the catcher, such as by removing submicron colloidal particles from the feed fluid and/or from the byproduct fluid. For example, the treatment assembly can include a coagulation unit, such as a chemical coagulation unit or an electrocoagulation unit, configured to coagulate the submicron colloidal particles. The pressurizing device, the cutting head, and the treatment assembly can be at different respective portions of a fluid-recycling loop.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 25, 2015
    Applicant: OMAX CORPORATION
    Inventors: Chidambaram Raghavan, Tanner Coker, Scott Thomas, James M. O'Connor, John H. Olsen
  • Patent number: 9065651
    Abstract: A base station (103) assigns a set of mobile stations (101) to a group wherein the group will share a set of radio resources (770). A shared control channel information element (501) is sent to the group of mobile stations (101) and provides a bitmap having fields for group ordering (511), resource allocations (530), continuation resources (540) for HARQ, and an ordering pattern (513). If a mobile station requires retransmission it will access the resources indicated by the continuation resources field (54) in order to receive data. The HARQ blocks may be assigned to a mobile station based upon an index (601) which may correspond to the mobile station vocoder rate. Further, HARQ subgroups may be defined to associate subgroups of mobile stations with specific HARQ transmission opportunities on the super-frame and allocated by a rotating bitmap.
    Type: Grant
    Filed: August 11, 2006
    Date of Patent: June 23, 2015
    Assignee: Google Technology Holdings LLC
    Inventors: Jack A. Smith, Hao Bi, Sean M. McBeath, James M. O'Connor, Danny T. Pinckley, John D. Reed
  • Patent number: 9021207
    Abstract: In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: April 28, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: John Kalamatianos, Edward J. McLellan, Paul Keltcher, Srilatha Manne, Richard E. Klass, James M. O'Connor
  • Patent number: 9011204
    Abstract: A waterjet system in accordance with a particular embodiment includes a pressurizing device configured to pressurize a fluid, a cutting head downstream from the pressurizing device, and a catcher positioned to collect a jet from the cutting head. The system can further include a treatment assembly configured to treat a feed fluid to the pressurizing device and/or a byproduct fluid from the catcher, such as by removing submicron colloidal particles from the feed fluid and/or from the byproduct fluid. For example, the treatment assembly can include a coagulation unit, such as a chemical coagulation unit or an electrocoagulation unit, configured to coagulate the submicron colloidal particles. The pressurizing device, the cutting head, and the treatment assembly can be at different respective portions of a fluid-recycling loop.
    Type: Grant
    Filed: March 27, 2014
    Date of Patent: April 21, 2015
    Assignee: OMAX Corporation
    Inventors: Chidambaram Raghavan, Tanner Coker, Scott Thomas, James M. O'Connor, John H. Olsen
  • Publication number: 20150100758
    Abstract: A data processor includes a register file divided into at least a first portion and a second portion for storing data. A single instruction, multiple data (SIMD) unit is also divided into at least a first lane and a second lane. The first and second lanes of the SIMD unit correspond respectively to the first and second portions of the register file. Furthermore, each lane of the SIMD unit is capable of data processing. The data processor also includes a realignment element in communication with the register file and the SIMD unit. The realignment element is configured to selectively realign conveyance of data between the first portion of the register file and the first lane of the SIMD unit to the second lane of the SIMD unit.
    Type: Application
    Filed: October 3, 2013
    Publication date: April 9, 2015
    Applicant: ADVANCED MICRO DEVICES, INC.
    Inventors: Timothy G. Rogers, Bradford M. Beckmann, James M. O'Connor
  • Publication number: 20150067691
    Abstract: A system, method, and computer program product are provided for providing prioritized access for multithreaded processing. The method includes the steps of allocating threads to process a workload and assigning a set of priority tokens to at least a portion of the threads. Access to a resource, by each one of the threads, is based on the priority token assigned to the thread and the threads are executed by a multithreaded processor to process the workload.
    Type: Application
    Filed: January 3, 2014
    Publication date: March 5, 2015
    Applicant: NVIDIA Corporation
    Inventors: Daniel Robert Johnson, Minsoo Rhu, James M. O' Connor, Stephen William Keckler
  • Publication number: 20150038055
    Abstract: A waterjet system in accordance with a particular embodiment includes a pressurizing device configured to pressurize a fluid, a cutting head downstream from the pressurizing device, and a catcher positioned to collect a jet from the cutting head. The system can further include a treatment assembly configured to treat a feed fluid to the pressurizing device and/or a byproduct fluid from the catcher, such as by removing submicron colloidal particles from the feed fluid and/or from the byproduct fluid. For example, the treatment assembly can include a coagulation unit, such as a chemical coagulation unit or an electrocoagulation unit, configured to coagulate the submicron colloidal particles. The pressurizing device, the cutting head, and the treatment assembly can be at different respective portions of a fluid-recycling loop.
    Type: Application
    Filed: March 27, 2014
    Publication date: February 5, 2015
    Applicant: OMAX CORPORATION
    Inventors: Chidambaram Raghavan, Tanner Coker, Scott Thomas, James M. O'Connor, John H. Olsen
  • Patent number: 8949544
    Abstract: The described embodiments include a computing device that handles memory requests. In some embodiments, when a memory request is to be sent to a cache in the computing device or to be bypassed to a next lower level of a memory hierarchy in the computing device based on expected memory request resolution times, a bypass mechanism is configured to send the memory request to the cache or bypass the memory request to the next lower level of the memory hierarchy.
    Type: Grant
    Filed: December 14, 2012
    Date of Patent: February 3, 2015
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Jaewoong Sim, James M. O'Connor
  • Publication number: 20150026511
    Abstract: A method and a system are provided for partitioning a system data bus. The method can include partitioning off a portion of a system data bus that includes one or more faulty bits to form a partitioned data bus. Further, the method includes transferring data over the partitioned data bus to compensate for data loss due to the one or more faulty bits in the system data bus.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 22, 2015
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Gabriel H. Loh, Yi Xu, James M. O'Connor
  • Publication number: 20150019813
    Abstract: A system includes a first memory and a device coupleable to the first memory. The device includes a second memory to cache data from the first memory. The second memory includes a plurality of rows, each row including a corresponding set of compressed data blocks of non-uniform sizes and a corresponding set of tag blocks. Each tag block represents a corresponding compressed data block of the row. The device further includes decompression logic to decompress data blocks accessed from the second memory. The device further includes compression logic to compress data blocks to be stored in the second memory.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Gabriel H. Loh, James M. O'Connor
  • Publication number: 20150019834
    Abstract: A system includes a device coupleable to a first memory. The device includes a second memory to cache data from the first memory. The second memory is to store a set of compressed pages of the first memory and a set of page descriptors. Each compressed page includes a set of compressed data blocks. Each page descriptor represents a corresponding page and includes a set of location identifiers that identify the locations of the compressed data blocks of the corresponding page in the second memory. The device further includes compression logic to compress data blocks of a page to be stored to the second memory and decompression logic to decompress compressed data blocks of a page accessed from the second memory.
    Type: Application
    Filed: July 11, 2013
    Publication date: January 15, 2015
    Inventors: Gabriel H. Loh, James M. O'Connor
  • Publication number: 20150016172
    Abstract: An integrated circuit (IC) package includes a stacked-die memory device. The stacked-die memory device includes a set of one or more stacked memory dies implementing memory cell circuitry. The stacked-die memory device further includes a set of one or more logic dies electrically coupled to the memory cell circuitry. The set of one or more logic dies includes a query controller and a memory controller. The memory controller is coupleable to at least one device external to the stacked-die memory device. The query controller is to perform a query operation on data stored in the memory cell circuitry responsive to a query command received from the external device.
    Type: Application
    Filed: July 15, 2013
    Publication date: January 15, 2015
    Inventors: Gabriel H. Loh, Nuwan S. Jayasena, James M. O'Connor, Yasuko Eckert
  • Patent number: 8923321
    Abstract: A base station (103) assigns a set of mobile stations (101) to a group wherein the group will share a set of radio resources (710). A shared control channel information element (501) is sent to the group of mobile stations (101) and provides a bitmap having fields for group ordering (511), resource allocations (530), failure handling resources (540), and an ordering pattern (513). If a mobile station fails to decode the shared control channel information element (501) it will access the failure handling resources in order to receive data. The failure handling channel may be persistent in some embodiments, or may be released after the mobile station is once again able to decode the shared control channel information element (501) and thereby share in the shared resource pool allocated to its mobile station group.
    Type: Grant
    Filed: July 28, 2006
    Date of Patent: December 30, 2014
    Assignee: Motorola Mobility LLC
    Inventors: Jack A. Smith, Hao Bi, Sean M. McBeath, James M. O'Connor, Danny T. Pinckley, John D. Reed