Patents by Inventor James O. Bondi

James O. Bondi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6401212
    Abstract: In a computer system (10) embodiment, there is included a memory (18) and circuitry (16a) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (14), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (16b, 16n, 17) using the system resource. The system further includes circuitry (20, 22, 24) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (26) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.
    Type: Grant
    Filed: November 8, 2000
    Date of Patent: June 4, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: James O. Bondi, Jonathan H. Shiell
  • Patent number: 6173410
    Abstract: In a computer system (10) embodiment, there is included a memory (18) and circuitry (16a) for prefetching information from the memory in response to a prefetch request. The system further includes a system resource (14), wherein the system resource is burdened in response to a prefetch operation by the circuitry for prefetching information. The system resource is also further burdened in response to other circuitry (16b, 16n, 17) using the system resource. The system further includes circuitry (20, 22, 24) for determining a measure of the burden on the system resource. Lastly, the system includes circuitry (26) for prohibiting prefetching of the information by the circuitry for prefetching information responsive to a comparison of the measure of the burden with a threshold. Other circuits, systems, and methods are also disclosed and claimed.
    Type: Grant
    Filed: August 21, 1997
    Date of Patent: January 9, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: James O. Bondi, Jonathan H. Shiell
  • Patent number: 6119222
    Abstract: A microprocessor (10) and corresponding system (300) is disclosed in which prefetch of instruction or data from higher level memory (11; 307; 305) may be performed in combination with a fetch from a lower level cache (16). A branch target buffer (56) has a plurality of entries (63) associated with branching instructions; in addition to the tag field (TAG) and target field (TARGET), each entry (63) includes prefetch fields (PF0 ADDR; PF1 ADDR) containing the addresses of memory prefetches that are to be performed in combination with the fetch of the branch target address. Graduation queue and tag check circuitry (27) is provided to update the contents of the prefetch fields (PF0 ADDR; PF1 ADDR) by interrogating instructions that are executed following the associated branching instruction to detect instructions that involve cache misses, in particular the target of the next later branching instruction.
    Type: Grant
    Filed: December 19, 1997
    Date of Patent: September 12, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Jonathan H. Shiell, James O. Bondi
  • Patent number: 6061811
    Abstract: A microprocessor (10) operating in response to a clock signal (CLK) having a clock period. The microprocessor includes a readable memory (16), and this readable memory stores code (BIST) for performing diagnostic evaluations of the microprocessor. The diagnostic evaluations include a first evaluation to occur under non-failure operation at a first clock period (24) and a last evaluation to occur under non-failure operation at a last clock period (26). The microprocessor further includes circuitry (14) for issuing a series of addresses to the readable memory in order to address the code for performing diagnostic evaluations of the microprocessor. Still further, the microprocessor includes a conductor (D0) externally accessible and for providing a signal from the microprocessor. Lastly, the microprocessor includes circuitry (12) for outputting a diagnostic signal on the externally accessible conductor during performance of the diagnostic evaluations.
    Type: Grant
    Filed: October 31, 1997
    Date of Patent: May 9, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: James O. Bondi, Joel J. Graber, Donald E. Steiss, John M. Johnsen
  • Patent number: 5958046
    Abstract: A circuit (10) for producing a microprogram memory address (16). This circuit includes circuitry (18I, 18J) for selecting a plurality of condition codes. Additionally, the circuit includes logic circuitry (20) for producing a result by performing logic operations using as operands the selected plurality of condition codes. The result of the logic operations forms a first portion (LSB', or LSB' and NLSB') of the microprogram memory address.
    Type: Grant
    Filed: November 26, 1996
    Date of Patent: September 28, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: James O. Bondi, Jonathan H. Shiell
  • Patent number: 5881277
    Abstract: A microprocessor comprising an instruction pipeline (36) comprising a plurality of successive instruction stages. An instruction passes from a beginning stage (38), through a plurality of intermediary stages (40 through 52), and to an ending stage (54) of the plurality of successive instruction stages. The microprocessor also comprises a storage circuit (58) coupled to receive program thread information output from a first stage (48) of the intermediary stages. Still further, the microprocessor comprises selection circuitry (56) comprising a first input, a second input, and an output for outputting output information from its first and second inputs. The first input of the selection circuitry is coupled to receive output information output from the first stage. The second input of the selection circuitry is coupled to receive program thread information output from the storage circuit.
    Type: Grant
    Filed: June 13, 1997
    Date of Patent: March 9, 1999
    Assignee: Texas Instruments Incorporated
    Inventors: James O. Bondi, Simonjit Dutta, Ashwini K. Nanda