Patents by Inventor James P. Flynn

James P. Flynn has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9049020
    Abstract: Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.
    Type: Grant
    Filed: June 2, 2010
    Date of Patent: June 2, 2015
    Assignee: SYNOPSYS, INC.
    Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8589708
    Abstract: Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: November 19, 2013
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8526551
    Abstract: An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: September 3, 2013
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8477898
    Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: July 2, 2013
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin, Dino A. Toffolon, Jasjeet Singh
  • Patent number: 8208591
    Abstract: Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: June 26, 2012
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8184757
    Abstract: An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: May 22, 2012
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 8125245
    Abstract: Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.
    Type: Grant
    Filed: June 21, 2010
    Date of Patent: February 28, 2012
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Publication number: 20110311009
    Abstract: An on-die scope is described. The on-die scope can include one or more scope slicers, phase sweeping circuitry, voltage sweeping circuitry, and eye-diagram data collection circuitry. The clock and data recovery circuitry can receive an input signal, and output a recovered clock signal and a recovered bit-stream. The phase sweeping circuitry can receive the recovered clock signal, and output the scope clock signal by adding a phase offset to the recovered clock signal. A scope slicer can receive the voltage threshold, the scope clock signal, and the input signal, and output a scope bit-stream. The eye-diagram data collection circuitry can detect one or more bit-patterns in the recovered bit-stream, and modify values of one or more scope counters based solely or partly on the scope bit-stream and the recovered bit-stream.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Publication number: 20110310942
    Abstract: One embodiment of the present invention provides a phase-locked loop (PLL) for synthesizing a fractional frequency. The PLL can include a 1/N frequency divider, a voltage-controlled oscillator (VCO), a programmable phase mixer, and a phase detector. The programmable phase mixer can be coupled between an output of the VCO and an input of the frequency divider, wherein the programmable phase mixer is configured to receive the output clock signal from the VCO and generate a first clock signal of frequency f1 by varying a phase of the output clock signal. The frequency divider is configured to receive the first clock signal from the programmable phase mixer and generate a second clock signal of frequency f2=f1/N. The phase detector can receive a reference clock signal and the second clock signal as inputs, and the phase detector's output can be used to generate the control voltage for the VCO.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin, Dino A. Toffolon, Jasjeet Singh
  • Publication number: 20110310947
    Abstract: Systems and techniques for adapting and/or optimizing an equalizer of a receiver are described. The equalizer's behavior can be adjusted by modifying one or more equalization parameters. At the beginning of the adaptation and/or optimization process, the system can determine robust initial values for the one or more equalization parameters. The system can then adapt and/or optimize the equalizer by iteratively adjusting the one or more equalization parameters. Specifically, in each iteration, the system can use the receiver's clock and data recovery (CDR) circuitry to determine the number of early and late data transitions associated with one or more data patterns. Next, the system can adjust the one or more equalization parameters so that, for each data pattern in the one or more data patterns, the ratio between the number of early data transitions and the number of late data transitions is substantially equal to a desired value.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, Junqi Hua, Robert B. Lefferts, Richard H. Steeves, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Publication number: 20110309857
    Abstract: Some embodiments of the present invention provide a voltage-mode transmitter. The transmitter can include configuration circuitry, bias circuitry, and a set of driver slices. Each driver slice can include driver transistors which drive an output value. The outputs of each driver slice can be directly or capacitively coupled with the transmitter's outputs. Each driver slice can also include one or more impedance-matching transistors which are serially coupled to at least some of the driver transistors. The configuration circuitry can configure a subset of driver slices so that the down (or up) impedance of the transmitter is within a first tolerance of a desired impedance value. The bias circuitry can bias the one or more impedance-matching transistors in each driver slice in the subset of driver slices so that the up (or down) impedance is within a second tolerance of the down (or up) impedance.
    Type: Application
    Filed: June 21, 2010
    Publication date: December 22, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Publication number: 20110307722
    Abstract: Some embodiments provide a clock and data recovery (CDR) system to recover clock and data information from an analog signal. The CDR system may include an integral path and a proportional path that are part of an integral-proportional control loop. The integral path may be used to track frequency changes in a clock signal that is embedded in the analog signal, while the proportional path may be used to track phase changes in the clock signal that is embedded in the analog signal. The proportional path may be executed at a first clock frequency, while the integral path may be executed at a second clock frequency that is lower than the first clock frequency to reduce the power consumption of the CDR system.
    Type: Application
    Filed: June 9, 2010
    Publication date: December 15, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Publication number: 20110302452
    Abstract: Circuitry to facilitate testing of serial interfaces is described. Specifically, some embodiments of the present invention facilitate testing the clock and data recovery functionality of a receiver. A serial interface can include a multiplying phase locked loop (MPLL) clock generator, a transmitter, and a receiver. The MPLL clock generator can generate a first clock signal and a second clock signal, and can vary a phase and/or frequency difference between the first clock signal and the second clock signal. During test, the transmitter and the receiver can be directly or capacitively coupled to each another. Specifically, during test, the serial interface can be configured so that the transmitter transmits data using the first clock signal, and the receiver receives data using the second clock signal. The clock and data recovery functionality of the receiver can be tested by comparing the transmitted data with the received data.
    Type: Application
    Filed: June 2, 2010
    Publication date: December 8, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Publication number: 20110292990
    Abstract: An integrated circuit that includes a receive data path is described. The receive data path: equalizes a received analog signal, converts the resulting equalized analog signal to digital data values based on a clock signal, and recovers the clock signal in the digital data values. The integrated circuit also includes an on-chip oscilloscope. The oscilloscope includes: two comparators, a phase rotator that outputs an oscilloscope clock signal whose phase can be varied relative to that of the recovered clock signal, and an offset circuit that outputs a voltage offset. Based on the voltage offset and the oscilloscope clock signal, the comparators output digital values which can be used to determine eye patterns that correspond to the analog signal before and after equalization. The eye patterns can then be correlated with an error rate associated with the received data.
    Type: Application
    Filed: June 1, 2010
    Publication date: December 1, 2011
    Applicant: SYNOPSYS, INC.
    Inventors: James P. Flynn, Junqi Hua, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 7995622
    Abstract: A method for digital clock smoothing is provided. The method comprises: (A) inputting an asynchronous data stream having an asynchronous symbol rate into a FIFO two-port memory block; (B) obtaining FIFO depth B by subtracting modulo B for each stored symbol a symbol output address from a symbol input address; (C) inputting FIFO depth B into a programmable look-up table (LUT); (D) obtaining a phase detector error signal; (E) scaling the phase detector error signal to obtain a scaled error factor; (F) adding the scaled error factor to a nominal phase step to obtain a phase update; (G) obtaining a smoothed symbol rate; and (H) reading out each output symbol from FIFO under control of an output FIFO address control register at the smoothed symbol rate.
    Type: Grant
    Filed: October 5, 2009
    Date of Patent: August 9, 2011
    Assignee: Wideband Semiconductor, Inc.
    Inventors: Richard John Fagerlund, James P. Flynn, Mark Fong, David Bruce Isaksen
  • Patent number: 7994814
    Abstract: Some embodiments of the present invention provide a programmable transmitter which includes a set of drivers and one or more chains of configuration registers. Each driver is capable of being configured to perform a transmission function from a predetermined set of transmission functions. Each configuration register can correspond to a driver, and can store configuration data which is used to configure the corresponding driver. The programmable transmitter can include configuration circuitry which serially shifts configuration data into the one or more chains of configuration registers. The programmable transmitter can also include programming circuitry which can determine configuration data for each driver based partly or solely on a desired transmitter behavior.
    Type: Grant
    Filed: June 1, 2010
    Date of Patent: August 9, 2011
    Assignee: Synopsys, Inc.
    Inventors: James P. Flynn, John T. Stonick, Daniel K. Weinlader, Jianping Wen, Skye Wolfer, David A. Yokoyama-Martin
  • Patent number: 7945780
    Abstract: An apparatus for encrypting and decrypting an original data stream is provided. The apparatus comprises: a key including a key-algorithm, an interleaver having at least one dynamically changeable interleaving parameter, and a de-interleaver adapted to communicate with a communication channel.
    Type: Grant
    Filed: September 24, 2009
    Date of Patent: May 17, 2011
    Assignee: Wideband Semiconductor, Inc.
    Inventors: James P. Flynn, Boris G. Tankhilevich
  • Patent number: 7770010
    Abstract: A method for encrypting and decrypting an original data stream comprising: (A) transmitting a copy of a key to an interleaver and to a de-interleaver, wherein the key includes a key-algorithm configured to describe an evolution in time of at least one interleaving parameter; (B) interleaving the original data stream by using the interleaver, wherein the interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter; and (C) recovering the original data stream from the interleaved data stream propagated through the communication channel by using the de-interleaver adapted to communicate with the communication channel, wherein the de-interleaver compensates for a change in latency caused by at least one dynamically changeable interleaving parameter.
    Type: Grant
    Filed: October 14, 2007
    Date of Patent: August 3, 2010
    Assignee: Wideband Semiconductors Inc.
    Inventors: James P. Flynn, Boris G. Tankhilevich
  • Patent number: 7707664
    Abstract: A bathroom cleansing apparatus for use by individuals when taking a shower. The bathroom cleansing apparatus is an improved showerhead which is attached to a length of flex hose. The flex hose itself is not normally visible when the shower head is not in use, but rather, is attached to a spool that is axially mounted behind a shower wall. The flex hose winds around the spool a few times before being attached to an incoming water line. The spool itself is attached to a torsion spring, which will cause the apparatus to slowly pull any extra length of flex hose not being used back onto the spool for later use.
    Type: Grant
    Filed: February 21, 2006
    Date of Patent: May 4, 2010
    Inventor: James P. Flynn
  • Publication number: 20100072293
    Abstract: A steam control system. An illustrative embodiment of the steam control system includes a boiler, a steam outlet conduit communicating with the boiler, a steam control valve provided in the steam outlet conduit, a controller connected to the steam control valve and an outdoor temperature sensor connected to the controller.
    Type: Application
    Filed: November 30, 2009
    Publication date: March 25, 2010
    Inventors: Bernard Flynn, James P. Flynn