Patents by Inventor James R. Eaton
James R. Eaton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240094120Abstract: This invention relates to the preparation of N-(phosphonomethyl)glycine (“glyphosate”) from N-(phosphonomethyl)iminodiacetic acid (“PMIDA”), and more particularly to methods for control of the conversion of PMIDA, for the identification of reaction end points relating to PMIDA conversion and the preparation of glyphosate products having controlled PMIDA content.Type: ApplicationFiled: September 22, 2023Publication date: March 21, 2024Inventors: Leonard AYNARDI, David Z. BECHER, Robert E. BYRD, Eduardo Aurelio CASANOVA, James P. COLEMAN, David R. EATON, Walter K. GAVLICK, Eric A. HAUPFEAR, Oliver LERCH, Carl MUMFORD, Alfredo OBA, Stephen D. PROSCH, Peter E. ROGERS, Bart ROOSE, Mark D. SCAIA, Lowell R. SMITH, Donald D. SOLETA, John WAGENKNECHT
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Patent number: 7376004Abstract: A method for making magnetic random access memories (MRAM) isolates each and every memory cell in an MRAM array during operation until selected. Some embodiments use series connected diodes for such electrical isolation. Only a selected one of the memory cells will then conduct current between respective ones of the bit and word lines. A better, more uniform distribution of read and data-write data access currents results to all the memory cells. In another embodiment, this improvement is used to increase the number of rows and columns to support a larger data array. In a further embodiment, such improvement is used to increase operating margins and reduce necessary data-write voltages and currents.Type: GrantFiled: September 11, 2003Date of Patent: May 20, 2008Assignee: Samsung Electronics Co., Ltd.Inventors: James R. Eaton, Jr., Frederick A. Perner, Lung T. Tran, Kenneth J. Eldredge
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Patent number: 7161838Abstract: A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator. The gate electrode portion includes a diffusive conductor that diffuses through the insulator under the application of a write voltage. The diffusive conductor forms a conductive path through the insulator that couples the gate line to the floating gate, changing the gate capacitance and therefore the state of the memory cell. The states of the memory cells are detectable as the differing current values for the memory cells. The memory cells are three terminal devices, and read currents do not pass through the conductive paths in the memory cells during read operations. This renders the memory cells robust, because read currents will not interfere with the storage mechanism in the memory cells. The memory array can be fabricated using multiple steps using the same mask.Type: GrantFiled: November 9, 2004Date of Patent: January 9, 2007Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ping Mei, James R Eaton, Jr.
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Patent number: 6927996Abstract: A magnetic random access memory (MRAM) includes an array of magnetic memory cells arranged on a cross-point grid. Spurious voltages that build up on the stray wiring capacitance of unselected bit and word select lines are limited and discharged by diodes. The control of such spurious voltages improves device operating margins and allows the construction of larger arrays.Type: GrantFiled: September 30, 2003Date of Patent: August 9, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: James R. Eaton, Jr., Kenneth J. Eldredge
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Patent number: 6864529Abstract: A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator. The gate electrode portion includes a diffusive conductor that diffuses through the insulator under the application of a write voltage. The diffusive conductor forms a conductive path through the insulator that couples the gate line to the floating gate, changing the gate capacitance and therefore the state of the memory cell. The states of the memory cells are detectable as the differing current values for the memory cells. The memory cells are three terminal devices, and read currents do not pass through the conductive paths in the memory cells during read operations. This renders the memory cells robust, because read currents will not interfere with the storage mechanism in the memory cells. The memory array can be fabricated using multiple steps using the same mask.Type: GrantFiled: August 23, 2001Date of Patent: March 8, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Ping Mei, James R. Eaton, Jr.
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Patent number: 6842389Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.Type: GrantFiled: January 17, 2003Date of Patent: January 11, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Frederick A. Perner, James R. Eaton, Jr., Kenneth K. Smith, Ken Eldredge, Lung Tran
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Patent number: 6839270Abstract: A control circuit for writing to and reading from MRAMs comprising a row decoder; a first read/write row driver connected to the row decoder; a plurality of global row write conductors connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductors.Type: GrantFiled: January 17, 2003Date of Patent: January 4, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: Frederick A. Perner, James R. Eaton, Jr., Kenneth K. Smith, Ken Eldredge, Lung Tran
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Patent number: 6781918Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. Address lines and power lines of each array are connected to the array so that only the data storage diode cells of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the array. A controller enables the row and column address lines to selectively address a diode cell in a selected array.Type: GrantFiled: February 10, 2004Date of Patent: August 24, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: James R. Eaton, Jr., Michael C. Fischer
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Publication number: 20040160844Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. The address lines and power lines of the plurality of arrays are connected to the arrays so that only the data storage diode cells in the array of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the data storage unit.Type: ApplicationFiled: February 10, 2004Publication date: August 19, 2004Inventors: James R. Eaton, Michael C. Fischer
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Publication number: 20040141365Abstract: A four-conductor MRAM device comprising an array of memory cells, each of the memory cells including a first magnetic layer, a dielectric, and a second magnetic layer; a plurality of local column sense lines wherein one is electrically connected to the first magnetic layer of the array of memory cells; a plurality of local row sense lines wherein one of the local row sense lines is electrically connected to the second magnetic layer of the array of memory cells; a plurality of global column write lines parallel to the plurality of local column sense lines; a plurality of global row write lines parallel to the plurality of local row sense lines; and wherein the plurality of local column sense lines and the plurality of local row sense lines are connected to read data from the array of memory cells and the plurality of global column write lines and the plurality of global row write lines are connected to write data to the array of memory cells.Type: ApplicationFiled: January 17, 2003Publication date: July 22, 2004Inventors: Frederick A. Perner, James R. Eaton, Kenneth K. Smith, Ken Eldredge, Lung Tran
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Publication number: 20040141364Abstract: A control circuit for writing to and reading from MRAMs comprising a row decoder; a first read/write row driver connected to the row decoder; a plurality of global row write conductors connected to the first read/write row driver; a plurality of row taps connected to each of the global row write conductors; and a second read/write row driver connected to the global row write conductors.Type: ApplicationFiled: January 17, 2003Publication date: July 22, 2004Inventors: Frederick A. Perner, James R. Eaton, Kenneth K. Smith, Ken Eldredge, Lung Tran
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Patent number: 6760245Abstract: A nano-scale flash memory comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region; (b) gate electrodes in a plurality of approximately parallel second wires, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the first wires with the second wires. Additionally, crossed-wire transistors are provided that can either form a configurable transistor or a switch memory bit that is capable of being set by application of a voltage. The crossed-wire transistors can be formed in a crossbar array.Type: GrantFiled: May 1, 2002Date of Patent: July 6, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: James R. Eaton, Jr., Philip John Kuekes
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Patent number: 6738307Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. Address lines and power lines of each array are connected to the array so that only the data storage diode cells of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the array. A controller enables the row and column address lines to selectively address a diode cell in a selected array.Type: GrantFiled: May 13, 2002Date of Patent: May 18, 2004Assignee: Hewlett-Packard Development Company, L.P.Inventors: James R. Eaton, Jr., Michael C. Fischer
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Publication number: 20040088471Abstract: A data storage device that includes an array of resistive memory cells and a circuit that is electrically connected to the array. The resistive memory cells include magnetic random access memory cells that are electrically connected to diodes. The circuit is capable of applying a first voltage to some of the resistive memory cells in the array, a second voltage to other cells in the array, and a third voltage to yet other cells in the array. Also, a method of sensing the resistance state of a selected resistive memory cell using the circuit.Type: ApplicationFiled: October 30, 2003Publication date: May 6, 2004Inventors: Frederick A. Perner, Lung T. Tran, James R. Eaton
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Patent number: 6661704Abstract: A method of and apparatus for connecting the sense current line in a cross-point memory array greatly reduces the effect of reverse leakage from unaddressed row or column lines. Separate sense line segments are coupled to separate stripes of row or column lines. Each sense line segment is connected to a sense diode, and each sense diode is connected to a sense bus. Each sense diode provides the current path for sensing on a selected row or column line, while allowing the leakage of only one diode per sense line segment for the unaddressed row or column lines. This arrangement results in wider margins for sensing the state of data cells in a cross-point memory array and simpler circuitry design for the memory array.Type: GrantFiled: December 10, 2001Date of Patent: December 9, 2003Assignee: Hewlett-Packard Development Company, L.P.Inventor: James R. Eaton, Jr.
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Publication number: 20030218905Abstract: A data storage device that includes an array of resistive memory cells and a circuit that is electrically connected to the array. The resistive memory cells include magnetic random access memory cells that are electrically connected to diodes. The circuit is capable of applying a first voltage to some of the resistive memory cells in the array, a second voltage to other cells in the array, and a third voltage to yet other cells in the array. Also, a method of sensing the resistance state of a selected resistive memory cell using the circuit.Type: ApplicationFiled: May 22, 2002Publication date: November 27, 2003Inventors: Frederick A. Perner, Lung T. Tran, James R. Eaton
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Publication number: 20030210568Abstract: An electrically addressable data storage unit has a matrix of rows and columns of data storage arrays on a single substrate. Each array is a matrix of coplanar data storage diode cells connected by row lines and column lines for recording, addressing and reading of data. The address lines and power lines of the plurality of arrays are connected to the arrays so that only the data storage diode cells in the array of a selected data storage cell are enabled, thereby eliminating undesirable power dissipation in all other arrays of the data storage unit.Type: ApplicationFiled: May 13, 2002Publication date: November 13, 2003Inventors: James R. Eaton, Michael C. Fischer
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Publication number: 20030206436Abstract: A nano-scale flash memory comprises: (a) source and drain regions in a plurality of approximately parallel first wires, the first wires comprising a semiconductor material, the source and drain regions separated by a channel region; (b) gate electrodes in a plurality of approximately parallel second wires, the second wires comprising either a semiconductor material or a metal, the second wires crossing the first wires at a non-zero angle over the channel regions, to form an array of nanoscale transistors; and (c) a hot electron trap region at each intersection of the first wires with the second wires. Additionally, crossed-wire transistors are provided that can either form a configurable transistor or a switch memory bit that is capable of being set by application of a voltage. The crossed-wire transistors can be formed in a crossbar array.Type: ApplicationFiled: May 1, 2002Publication date: November 6, 2003Inventors: James R. Eaton, Philip John Kuekes
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Publication number: 20030107917Abstract: A method and apparatus of connecting the sense current lines in a cross-point memory array which greatly reduces the effect of reverse leakage from unaddressed row or column lines. Separate sense line segments are coupled to separate stripes of row or column lines. Each sense line segment is connected to a sense diode, and each sense diode is connected to a sense bus. Each sense diode provides the current path for sensing on a selected row or column line, while allowing the leakage of only one diode per sense line segment for the unaddressed row or column lines. This arrangement results in wider margins for sensing the state of data cells in a cross-point memory array and simpler circuitry design for the memory array.Type: ApplicationFiled: December 10, 2001Publication date: June 12, 2003Inventor: James R. Eaton
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Publication number: 20030045037Abstract: A memory device includes a memory array of thin film transistor (TFT) memory cells. The memory cells include a floating gate separated from a gate electrode portion of a gate line by an insulator. The gate electrode portion includes a diffusive conductor that diffuses through the insulator under the application of a write voltage. The diffusive conductor forms a conductive path through the insulator that couples the gate line to the floating gate, changing the gate capacitance and therefore the state of the memory cell. The states of the memory cells are detectable as the differing current values for the memory cells. The memory cells are three terminal devices, and read currents do not pass through the conductive paths in the memory cells during read operations. This renders the memory cells robust, because read currents will not interfere with the storage mechanism in the memory cells. The memory array can be fabricated using multiple steps using the same mask.Type: ApplicationFiled: August 23, 2001Publication date: March 6, 2003Inventors: Ping Mei, James R. Eaton