Patents by Inventor James R. Larus

James R. Larus has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20080082480
    Abstract: A computing paradigm where information can be aggregated from multiple services/programs within a ‘cloud-based’ environment is provided. Thus, the system can provide a uniform interface that can combine computational tasks across the multiple services/programs. Thus, the innovation takes advantage of the computing device being a ‘thin client’ which affords greater user comfort to a user without sacrificing data processing capabilities. Accordingly, the mechanisms are disclosed that standardize and/or normalize data across the resources within the cloud.
    Type: Application
    Filed: September 29, 2006
    Publication date: April 3, 2008
    Applicant: MICROSOFT CORPORATION
    Inventors: Alexander G. Gounares, Thomas F. Bergstraesser, Christopher W. Brumme, Lili Cheng, James R. Larus, Henricus Johannes Maria Meijer, Debi P. Mishra, Ira L. Snyder
  • Publication number: 20080005750
    Abstract: Described herein are one or more implementations that separate kernel interfaces functions into those that act on kernel objects owned by a process and accessed exclusively by that process—described herein as local kernel objects—from access to kernel objects owned by a process and accessible_by other active processes.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Applicant: Microsoft Corporation
    Inventors: Galen C. Hunt, James R. Larus, Manuel A. Fahndrich, Bjarne Steensgaard, David R. Tarditi, Brian Zill
  • Publication number: 20070282572
    Abstract: A virtual machine is instantiated on an M-core processor, and an N-core application is instantiated on the virtual machine such that the virtual machine emulates an N-core processor to the N-core application. Thus, the virtual machine hides difference between the N cores expected by the application and the M cores available from the processor.
    Type: Application
    Filed: June 1, 2006
    Publication date: December 6, 2007
    Applicant: Microsoft Corporation
    Inventor: James R. Larus
  • Patent number: 7137116
    Abstract: A method and system for performing a task on a computer is provided, in which the procedure is organized into multiple stages. Each stage of the task has an associated sub-task. Requests for the procedure are represented by “work packets” that stored in a holding area at each stage, such as a stack or a queue, until it is advantageous for a processor to execute them. Each work packet contains data and/or instructions for performing the sub-task of the stage. When a processor is available, it finds a stage having unexecuted work packets and executes a batch of work packets by repeatedly performing the sub-task of the stage. This repeated execution of a sub-task allows a processor to maximize its native time-saving mechanisms, such as cache. The invention may advantageously be used as an alternative to conventional thread-based programming.
    Type: Grant
    Filed: February 8, 2001
    Date of Patent: November 14, 2006
    Assignee: Microsoft Corporation
    Inventors: Michael A Parkes, James R. Larus
  • Publication number: 20040172638
    Abstract: An asynchronous programming language that facilitates concurrent programming by utilizing futures, asynchronous calls, and joins on futures. For each of a client interface and a service interface of an asynchronous interface, respective models are automatically extracted. A behavioral contract is defined on the asynchronous interface. The client and service models are then passed to modular checking algorithm that checks to ensure that both the client and the service conform to the behavioral contract. The checking algorithm combines region-based type systems with model checking techniques to handle pointer aliasing in a sound manner.
    Type: Application
    Filed: September 10, 2003
    Publication date: September 2, 2004
    Inventors: James R. Larus, Sriram K. Rajamani, Jakob Rehof
  • Publication number: 20030204641
    Abstract: A system and method for developing a message-passing application program is disclosed. The message-passing application program is constructed using stages having a plurality of asynchronous functions, or operations. The operations communicate with other operations of other message-passing programs in a distributed computing environment. The operations also communicate with other operations on other stages of the message-passing application. In order to reduce deadlock errors that occur as a result of the asynchronous nature of these communications, a behavioral type signature is appended to the declaration of each operation of the message-passing application program. The behavioral type signature specifies behavioral properties for each operation, such as when an operation should send a message to another operation and, conversely, when an operation should wait for a message from another operation.
    Type: Application
    Filed: April 30, 2002
    Publication date: October 30, 2003
    Applicant: Microsoft Corporation
    Inventors: Jakob Rehof, James R. Larus, Sriram K. Rajamani
  • Patent number: 6360361
    Abstract: Fields which are individually addressable data elements in data structures are reordered to improve the efficiency of cache line access. Temporal data regarding the referencing of such fields is obtained, and a tool is used to construct a field affinity graph of temporal access affinities between the fields. Nodes in the graph represent fields, and edges between the nodes are weighted to indicate field affinity. A first pass greedy algorithm attempts to combine high affinity fields in the same cache line or block. Constraints are used to reject invalid combinations of fields. The constraints may be provided by program analysis, programmer, or actual dynamically generated.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: March 19, 2002
    Assignee: Microsoft Corporation
    Inventors: James R. Larus, Robert Davidson, Trishul M. Chilimbi
  • Patent number: 6330556
    Abstract: Fields which are individually addressable data elements in data structures are reordered to improve the efficiency of cache line access. Temporal data regarding the referencing of such fields is obtained, and a tool is used to construct a field affinity graph of temporal access affinities between the fields. Nodes in the graph represent fields, and edges between the nodes are weighted to indicate field affinity. A first pass greedy algorithm attempts to combine high affinity fields in the same cache line or block. Constraints are used to reject invalid combinations of fields. Data structures such as class are partitioned into heavily referenced and less heavily referenced portions. The partitioning is based on profile information about field access counts with indirect addressing used to reference the less heavily referenced partitioned class. A class co-location scheme is used to ensure that temporally correlated classes are placed near each other in cache blocks.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: December 11, 2001
    Inventors: Trishul M. Chilimbi, James R. Larus, Robert Davidson
  • Patent number: 6327699
    Abstract: A program is instrumented to record acyclic paths during execution of the program. A whole program path is produced from the record and provides a complete compact record of a program's entire control flow. It includes a record of crossing loop boundaries and procedure boundaries to provide a complete picture of the program's dynamic behavior. A string compression algorithm that constructs a context-free grammar is used to compress the path trace and uncover its regular structure. Heavily executed subpaths are easily identified from the representation by traversing the whole program path to find hot subpaths according to input parameters of minimum and maximum path lengths and a minimum cost.
    Type: Grant
    Filed: April 30, 1999
    Date of Patent: December 4, 2001
    Assignee: Microsoft Corporation
    Inventors: James R. Larus, Christopher W. Fraser
  • Patent number: 6321240
    Abstract: Fields which are individually addressable data elements in data structures are reordered to improve the efficiency of cache line access. Temporal data regarding the referencing of such fields is obtained, and a tool is used to construct a field affinity graph of temporal access affinities between the fields. Nodes in the graph represent fields, and edges between the nodes are weighted to indicate field affinity. A first pass greedy algorithm attempts to combine high affinity fields in the same cache line or block. Constraints are used to reject invalid combinations of fields. Data structures such as class are partitioned into heavily referenced and less heavily referenced portions. The partitioning is based on profile information about field access counts with indirect addressing used to reference the less heavily referenced partitioned class. A class co-location scheme is used to ensure that temporally correlated classes are placed near each other in cache blocks.
    Type: Grant
    Filed: March 15, 1999
    Date of Patent: November 20, 2001
    Inventors: Trishul M. Chilimbi, James R. Larus
  • Publication number: 20010005853
    Abstract: A method and system for performing a task on a computer is provided, in which the procedure is organized into multiple stages. Each stage of the task has an associated sub-task. Requests for the procedure are represented by “work packets” that stored in a holding area at each stage, such as a stack or a queue, until it is advantageous for a processor to execute them. Each work packet contains data and/or instructions for performing the sub-task of the stage. When a processor is available, it finds a stage having unexecuted work packets and executes a batch of work packets by repeatedly performing the sub-task of the stage. This repeated execution of a sub-task allows a processor to maximize its native time-saving mechanisms, such as cache. The invention may advantageously be used as an alternative to conventional thread-based programming.
    Type: Application
    Filed: February 8, 2001
    Publication date: June 28, 2001
    Inventors: Michael A. B. Parkes, James R. Larus