Abstract: A process for fabricating semiconductor devices is disclosed which utilizes a selective deposition process to reduce the total number of process steps and especially the total number of photolithography steps required. In accordance with one embodiment of the invention a semiconductor substrate is provided having an insulating layer, a nucleating layer, and a second insulating layer overlaying the substrate. A photoresist mask is used an implant mask and as an etch mask to expose a portion of nucleating layer. A second implant mask is formed by the selective deposition of tungsten or other material on the exposed nucleating layer. The selectively deposited material is then used a mask for a second implantation.

Abstract: A stacked shared-gate CMOS transistor and method of fabrication are disclosed. An improved CMOS transistor is fabricated by the formation of a bulk transistor and an overlying isolated (SOI) transistor wherein each transistor is adjoined to a portion of a shared gate having the same conductivity type as the related transistor. The differential conductivity of the shared gate is obtained by the fabrication of a conductive diffusion-barrier layer intermediate to conductive layers. Improved switching performance is obtained as a result of higher current levels produced by the isolated transistor.

Abstract: A process is disclosed for the fabrication of semiconductor devices which yields a device having a very short effective channel length and having polycrystalline source and drain electrodes. In accordance with the disclosed process, a semiconductor substrate is provided having a masking element positioned on the substrate surface. A layer of polycrystalline silicon is deposited on the exposed areas of the substrate surface by the process of selective deposition. The selectively deposited polycrystalline silicon is doped with conductivity determining impurities and that impurity material is thereafter redistributed to dope the underlying substrate to form source and drain regions. The masking element is removed to expose the portion of the semiconductor surface between the source and drain regions and to allow for a subsequent optional channel implantation.

Abstract: A process is disclosed for fabricating bipolar transistors having self aligned and closely spaced polycrystalline silicon base and emitter electrodes. The process is especially amenable to integration with the fabrication of MOS transistors to form BiMOS integrated circuits. In accordance with one embodiment of the invention, a P type polycrystalline silicon layer is deposited overlying an N type silicon substrate. The polycrystalline silicon layer is patterned to form base contact electrodes and to leave exposed a portion of the surface of the N-type substrate. An electrically insulating layer is formed overlying the polycrystalline silicon base contacts and the exposed silicon substrate. Sidewall spacers are formed on the electrically insulating layer at the sidewalls of the base contact electrode.

Abstract: In forming a lightly-doped drain (LDD) transistor there is first formed a thin polysilicon layer over a gate oxide on an active region. A masking layer is deposited and selectively etched to expose a middle portion of the polysilicon layer. This structure can be used as part of a process which results in a formation of an inverse-T transistor or a conventional LDD structure which is formed by disposable sidewall spacers. The exposed middle portion of the polysilicon layer is used to form a polysilicon gate by selective polysilicon deposition. The exposed middle portion can be implanted through for the channel implant, thus providing self-alignment to the source/drain implants. Sidewall spacers can be formed inside the exposed portion to reduce the channel length. These sidewall spacers can be nitride to provide etching selectivity between the sidewall spacer and the conveniently used low temperature oxide (LTO) mask.

Abstract: An LDD transistor is formed by using a process which insures that a layer of gate oxide is not inadvertently etched into and is not ruptured by static electrical charges. At least two thicknesses of gate electrode material of varying doping levels are formed over a layer of gate oxide which is above a semiconductor substrate. A chemical etch is utilized wherein by monitoring a ratio of chemical product and chemical reactant of the chemical etch reactions, specific endpoints in the etching of the gate electrode material can be easily detected. A small layer of gate electrode material is allowed to remain over the gate oxide layer during ion implanting and the formation and removal of gate sidewall spacers used in fabricating an LDD transistor. After formation of most of the LDD transistor, the remaining protective thickness of gate electrode material is removed and the exposed gate oxide layer is exposed to a final oxidizing anneal step.

Abstract: A semiconductor device structure including a contact and a method for its fabrication are disclosed. In accordance with one embodiment of the disclosure, a contact is formed between a monocrystalline silicon substrate and an overlying silicon layer. A silicon substrate is provided which has a first insulating layer formed thereon. A layer of silicon is deposited and patterned over the insulator layer. The patterned silicon layer is then oxidized and a contact opening is etched through the first insulator layer and the silicon dioxide is expose portions of the silicon substrate and an adjacent portion of the patterned silicon layer. A further layer of polycrystalline silicon is then selectively deposited onto the exposed portions of the substrate and silicon layer to form an electrical connection between the two.

Abstract: A process for fabricating an integrated circuit resistor is disclosed. In accordance with one embodiment of that invention a first thin layer of silicon is deposited to overlay a semiconductor substrate. That thin layer of silicon is doped to a predetermined level to establish the proper conductivity desired for the integrated circuit resistor being formed. The first layer of silicon is patterned to form a first resistor layer and a second interconnect area with the two areas being in contact. A layer of insulating material is formed over the resistor area to mask the resistor area from subsequent processing steps. A second layer of silicon is deposited by a process of selective deposition onto the exposed interconnect areas of the first thin layer of silicon and that selectively deposited silicon is heavily doped with conductivity determining impurity material to reduce the resistivity thereof.

Abstract: A process for the fabrication of elevated source/drain IGFET devices is disclosed. In accordance with one embodiment of the process, a silicon substrate is provided which is divided into active and field regions by a field oxide. A gate oxide is formed over the active region and a thin layer of polycrystalline silicon and a thick layer of silicon nitride are deposited on the gate oxide. The polycrystalline silicon and the silicon nitride are etched to form a stacked structure, with the spacers having substantially the same height as the stacked structure, in the pattern of the gate electrode. Sidewall spacers are formed on the edges of the stacked structure and the silicon nitride is removed. Polycrystalline silicon is then deposited onto the polycrystalline silicon and the exposed portions of the source and drain regions to complete the gate electrode and to form the source and drain electrodes.

Abstract: A method for fabricating a self-aligned trench structure in a semiconductor device is disclosed. In accordance with one method for fabricating the trench structure, an oxidation resistant material having an opening is used as a masking layer. The edge of the opening in the masking layer is covered by a sidewall spacer which protects a portion of the substrate from attack by the etchant used to form the trench. The trench is filled with a trench fill material by selective deposition using a seeding material formed on the sidewall of the trench as a nucleation site. After the trench is filled, the sidewall spacer is removed and the underlying substrate is oxidized to form an electrical insulation region around the upper portion of the trench. The mask layer is removed and the remaining substrate is doped using the insulation region surrounding the trench as a dopant mask.

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n.sup.- and n.sup.+ regions in GSDs and LDDs.

Abstract: A compact CMOS structure and method for fabricating the structure are disclosed. In one embodiment of the invention the structure includes a P-type surface region in a silicon substrate surrounded by a field oxide which extends, at least in part, above the surface of the substrate. A polycrystalline silicon sidewall frame is formed at the sidewall of the field oxide and a gate insulator is formed over both the polycrystalline silicon frame and the silicon surface region. A common gate electrode is formed which traverses the frame and the surface region. P-type source and drain regions are formed in the polycrystalline silicon frame on opposite sides of the gate electrode and N-type source and drain regions are formed in the surface region on opposite sides of the gate electrode.

Abstract: A process for fabricating a CMOS device using one sidewall spacer for both the source/drain implant and salicide formation, thereby providing an improved salicided source/drain structure. The use of one sidewall spacer for both the source/drain implant and the silicide formation facilitates the closer spacing of the silicide region to the gate edge. Prior to the salicidation, a silicon overetch is performed to remove the P+ implant in the source/drain and poly regions of the NMOST. The silicon overetch forms a concave surface on the N+ source/drain regions, which allows salicide formation closer to the edge of the channel. Due to the proximity of the edge of the silicide to the edge of the channel, the series resistance of the NMOST is significantly reduced.

Abstract: An erasable programmable read only memory (EPROM) cell having a floating gate and a control gate where the floating gate and the control gate are deliberately offset or asymmetrical from the source/drain and drain/source regions in the substrate. During programming, the source region is the one spaced apart from the gates while the drain region is aligned thereto. This orientation produces high gate currents to provide faster programming. During a read operation the aligned region now becomes the source and the spaced apart region becomes the drain to provide high drain currents for fast access. The asymmetrical EPROM cells of the present invention may be readily made using conventional spacer technology.

Abstract: A process is disclosed for the selective oxidation of MOS devices which preferentially removes implanted field doping from selected silicon substrate regions. In one embodiment, a CMOS substrate is provided with an overlying layer of silicon oxide and a layer of polycrystalline silicon. Active and field regions are defined in each of the CMOS device regions. A blanket boron implantation dopes both the N-type and P-type field regions. The N-type field region is selectively oxidized at a greater oxidation rate than is the P-type field region to cause a greater segregation of boron impurities into the growing oxide over the N-type field region. Regions of enhanced boron doping are thus formed under the field oxide in the P-type region, but not in the N-type region.

Abstract: Metal-oxide-semiconductor (MOS) transistors with n-type source/drain regions also having germanium-doped regions in or near the source/drains. The presence of germanium near or at the location of phosphorus in graded source drains (GSDs), lightly doped drains (LDDs) and double diffused drains (DDDs) gives a better profile of the drain region with a reduced junction depth than that obtainable with phosphorus or particularly phosphorus and arsenic together. Good grading of the drain junction to avoid hot carrier instability or hot carrier injection problems is obtained along with shallow source junctions, which minimizes lateral dopant diffusion and decreases the distance between n- and n+ regions in GSDs and LDDs.

Abstract: A salicided twin-tub CMOS process using germanium implantation to retard the diffusion of the dopants, such as phosphorus and boron. Implantation of n+ and p+ dopants after titanium salicidation is employed to fabricate devices with low junction leakage and good short-channel effects. Also, the germanium dopant may be introduced before or after the formation of the refractory metal silicide formation, and may be implanted independently or together with the dopant whose diffusion in the silicon it will modify. The employment of germanium permits the use of a phosphorus implant through a relatively thick refractory metal silicide contact layer. If arsenic is implanted through the silicide layer to solve the deep junction problem, the silicide layer must be thin to permit the passage of the larger arsenic atoms typically stopped by the silicide. Thinner silicide layers have the disadvantage of higher sheet resistances.

Abstract: A random access memory (RAM) cell of a trench within a semiconductor substrate. The RAM cell has a load device in the form of a sidewall around at least part of the perimeter of the trench. The load device should be connected to either one of the source/drain regions or the gate in a field effect transistor (FET). If the load device is a capacitor, using the sidewall structure as one plate and the wall of the trench as the other plate, with a thin dielectric layer between, then a dynamic RAM cell (DRAM) cell with result. On the other hand, if the sidewall load device is a resistor, then a static RAM cell or SRAM will result. The compact nature of the trench sidewall load structure will consume appreciably less lateral space than conventional RAM cells. Additionally, the gate for the FET in the bottom floor of the trench can be formed at the same time and out of the same conductive layer as the conductive sidewall load device, an advantage which saves process steps.

Abstract: An electronic process is provided for creating a small dimensioned pattern in a semiconductor device. In one embodiment, the pattern functions to electrically separate two areas of the substrate by less than a micron. A lithographic mask which does not have to utilize dimensions as small as those being formed on the semiconductor device is used to form a predetermined pattern with at least one separation region by irradiating and developing a photoresist material. A layer of buffer material below the photoresist material reacts with a reactive ion etch to form a separation area with sloping sides comprised of polymer filaments produced from the reaction. The sloped sides of the separation region provide a separation dimension in the substrate of the semiconductor structure which is significantly smaller than a corresponding dimension required to be implemented on the lithographic mask.

Abstract: A compact, multi-state field effect transistor (FET) cell having a gate with edge portions of a different conductivity type than a central portion of the gate. Both the edge portions and the central portion extend from the source to the drain of the multi-state FET device. This device would have two different threshold voltages (V.sub.T), one where the central portion would turn on first, followed by the edges for the entire gate width to be active to give a second level of current flow. Such devices would be useful in building very compact or high density multi-state read-only-memories (ROMs).