Patents by Inventor James Robert Feddeler

James Robert Feddeler has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11128306
    Abstract: A clock generation circuit includes a switched capacitor circuit for providing a discrete amount of charge to a resonator for sustaining energization of the resonator at specific portions of the clock cycle.
    Type: Grant
    Filed: July 15, 2020
    Date of Patent: September 21, 2021
    Assignee: NXP USA, INC.
    Inventors: Stefano Pietri, Juan Camilo Monsalve, Ricardo Pureza Coimbra, James Robert Feddeler
  • Patent number: 10972096
    Abstract: An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: April 6, 2021
    Assignee: NXP USA, INC.
    Inventors: Robert Matthew Mertens, James Robert Feddeler, Michael A. Stockinger
  • Publication number: 20200412363
    Abstract: An electronic switch that includes a signal path with a first terminal side of the signal path including cascoded transistors in the signal path. When the switch is in an off state, the gate of one of the cascoded transistors is biased at an intermediate voltage different from the voltage applied to the gate of the other of the cascoded transistors. In one embodiment, having the gate of one of the cascoded transistors biased at an intermediate voltage in an off state may reduce leakage current into a signal terminal of the switch. The electronic switch includes an injection shunting device (e.g. such as a transistor) connected to a node of the signal path. In one embodiment, the injection shunting device prevents the voltage of the node from reaching a specific voltage level due to leakage current when the switch is in an off state.
    Type: Application
    Filed: June 28, 2019
    Publication date: December 31, 2020
    Inventors: Robert Matthew Mertens, James Robert Feddeler, Michael A. Stockinger
  • Patent number: 10819279
    Abstract: A low power crystal oscillator is provided. The crystal oscillator includes a gain control stage, a filter stage, and an output stage. The gain control stage includes an input coupled at a first oscillator terminal configured and arranged for connection to a first terminal of a crystal. The filter stage includes an input coupled to an output of the gain control stage. The output stage includes a first transistor having a first current electrode coupled at a second oscillator terminal configured and arranged for connection to a second terminal of the crystal and a control electrode coupled to receive a voltage signal at the first oscillator terminal and a first bias voltage.
    Type: Grant
    Filed: June 28, 2019
    Date of Patent: October 27, 2020
    Assignee: NXP USA, INC.
    Inventors: Juan Camilo Monsalve, Ricardo Pureza Coimbra, James Robert Feddeler, Stefano Pietri
  • Patent number: 10790848
    Abstract: A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.
    Type: Grant
    Filed: January 1, 2019
    Date of Patent: September 29, 2020
    Assignee: NXP USA, Inc.
    Inventors: Yizhong Zhang, Stefano Pietri, James Robert Feddeler, Michael Todd Berens
  • Patent number: 10784886
    Abstract: A digital to analog converter receives a digital input consisting of first least significant bits, second most significant bits, and third middle significant bits. The digital to analog converter includes first, second, and third sub-DACs. The first sub-DAC receives the first least significant bits, and includes first resistors each contributing a respective voltage, to provide a first output. The second sub-DAC receives the second most significant bits, and includes second resistors each contributing a respective voltage, to provide a second output as an output of the digital to analog converter. The third sub-DAC is connected to the first sub-DAC to receive the first output, and receives the third middle significant bits, and includes third resistors each contributing a respective voltage, to provide a third output to the second sub-DAC. The first and third resistors each has a physical area less than an area of each second resistor.
    Type: Grant
    Filed: February 21, 2020
    Date of Patent: September 22, 2020
    Assignee: NXP USA, Inc.
    Inventors: Yizhong Zhang, Stefano Pietri, James Robert Feddeler, Michael Todd Berens
  • Patent number: 10659038
    Abstract: A method of powering up a circuit includes powering up a latch circuit in a known latch state by applying a first power supply voltage differential of a first voltage domain across power supply terminals of the latch circuit. A current diode inhibits current diode in a current path between a latch node of the latch circuit and a power supply terminal when the power supply voltage differential is below a threshold voltage during the powering up in which the inhibiting prevents the latch circuit from switching from the known latch state during the powering up.
    Type: Grant
    Filed: March 12, 2019
    Date of Patent: May 19, 2020
    Assignee: NXP USA, Inc.
    Inventors: Robert Matthew Mertens, James Robert Feddeler, Stefano Pietri
  • Patent number: 10509428
    Abstract: A first voltage scaling power switch is coupled to a first power supply terminal for providing power to a first circuit portion, and a second voltage scaling power switch is coupled between the first power supply terminal providing power to a second circuit portion. A common power rail is coupled the first and second power input nodes during respective voltage scaling modes of the first and second circuit portions. A feedback circuit coupled to the common power rail provides a feedback signal to a control input of the first voltage scaling power switch to regulate a voltage provided by the first power switch, and to a control input of the second voltage scaling power switch to regulate a voltage provided by the second voltage scaling power switch.
    Type: Grant
    Filed: April 29, 2019
    Date of Patent: December 17, 2019
    Assignee: NXP USA, INC.
    Inventors: Dale John McQuirk, Miten H. Nagda, Nidhi Chaudhry, James Robert Feddeler, Stefano Pietri, Simon Gallimore
  • Publication number: 20190372586
    Abstract: A digital to analog converter (DAC) that receives a binary coded signal and generates an analog output signal includes a binary-to-thermometer decoder and a resistive network. The decoder receives the binary coded signal, and decodes it into thermometer signals. The resistive network has branches that are coupled to an output terminal of the DAC in response to the thermometer signals. Each of the branches includes first and second resistors, and a switch. The first resistor is coupled between a first reference voltage and the switch, and the second resistor is coupled between a second reference voltage and the switch. The switch couples either the first resistor or the second resistor to the output terminal in response to a corresponding thermometer signal.
    Type: Application
    Filed: January 1, 2019
    Publication date: December 5, 2019
    Inventors: Yizhong Zhang, Stefano Pietri, James Robert Feddeler, Michael Todd Berens
  • Patent number: 10243577
    Abstract: An analog-to-digital converter (ADC) includes a split-capacitor digital-to-analog converter (DAC) having a Most Significant Bits (MSBs) sub-DAC with one or more MSBs encoded with one or more binary capacitors and one or more MSBs encoded with one or more thermometer capacitors, a Least Significant Bits (LSBs) sub-DAC, a termination capacitor coupled to the LSBs sub-DAC, and a scaling capacitor coupled between the LSBs and MSBs sub-DACs, and coupled to receive an analog input voltage, a high reference voltage, and a low reference voltage, and to provide an output voltage.
    Type: Grant
    Filed: April 2, 2018
    Date of Patent: March 26, 2019
    Assignee: NXP USA, Inc.
    Inventors: Michael Todd Berens, Khoi Mai, James Robert Feddeler
  • Patent number: 10110244
    Abstract: A digital to analog converter (DAC) includes a first sub-DAC configured to convert most significant bits (MSBs) of digital input data, the first sub-DAC including a first array of resistors, a second sub-DAC configured to convert at least some least significant bits (LSBs) of the digital input data, the second sub-DAC including a second array of resistors, and a first scaling resistor connected between the first and second sub-DACs, wherein the first scaling resistor has a resistance value that is based on the number of resistors in the second sub-DAC.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: October 23, 2018
    Assignee: NXP USA, Inc.
    Inventors: Stefano Pietri, James Robert Feddeler, Michael Todd Berens, Yizhong Zhang