Patents by Inventor James Spiros Nakos
James Spiros Nakos has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8236580Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.Type: GrantFiled: December 20, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
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Publication number: 20110278674Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.Type: ApplicationFiled: July 28, 2011Publication date: November 17, 2011Applicant: International Business Machines CorporationInventors: Terence Blackwell Hook, Jeffrey Bowman Johnson, James Spiros Nakos
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Patent number: 8012848Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.Type: GrantFiled: August 16, 2007Date of Patent: September 6, 2011Assignee: International Business Machines CorporationInventors: Terence Blackwell Hook, Jeffrey Bowman Johnson, James Spiros Nakos
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Patent number: 7957917Abstract: A computer system. The computer system including a processor and memory unit coupled to the processor, the memory unit containing instructions that when executed by the processor implement a method for monitoring a solution in a tank used to fabricate integrated circuits, the method comprising the computer implemented steps of: (a) collecting data indicating of an amount of copper in a region of a substrate of a monitor, the monitor comprising an N-type region in a silicon substrate, the region abutting a top surface of the substrate, the monitor having been submerged in the solution for a preset time; (b) comparing the data to a specification for copper content of the solution; (c) if the data indicates a copper content exceeds a limit of the specification for copper, indicating a corrective action is required to prevent copper contamination of the integrated circuits; and (d) repeating steps (a) through (c) periodically.Type: GrantFiled: September 28, 2007Date of Patent: June 7, 2011Assignee: International Business Machines CorporationInventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
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Publication number: 20110086442Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.Type: ApplicationFiled: December 20, 2010Publication date: April 14, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
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Patent number: 7897940Abstract: An apparatus. The apparatus including: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.Type: GrantFiled: July 7, 2008Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Alan Michael Chandler, Tushar Desai, Ellis Craig Hayford, Nicholas Mone, Jr., James Spiros Nakos
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Patent number: 7897939Abstract: A method of improving the performance of charged beam apparatus. The method including: providing the apparatus, the apparatus comprising: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; and a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and positioning one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.Type: GrantFiled: July 3, 2008Date of Patent: March 1, 2011Assignee: International Business Machines CorporationInventors: Alan Michael Chandler, Tushar Desai, Ellis Craig Hayford, Nicholas Mone, Jr., James Spiros Nakos
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Patent number: 7888142Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.Type: GrantFiled: September 28, 2007Date of Patent: February 15, 2011Assignee: International Business Machines CorporationInventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
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Patent number: 7737050Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.Type: GrantFiled: October 30, 2006Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Edward Dennis Adams, Jay Sanford Burnham, Evgeni Gousev, James Spiros Nakos, Heather Elizabeth Preuss, Joseph Francis Shepard, Jr.
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Publication number: 20090087928Abstract: A method of monitoring copper contamination. The method includes method, comprising: (a) ion-implanting an N-type dopant into a region of single-crystal silicon substrate, the region abutting a top surface of the substrate; (c) activating the N-type dopant by annealing the substrate at a temperature of 500° C. or higher in an inert atmosphere; (c) submerging, for a present duration of time, the substrate into an aqueous solution, the aqueous solution to be monitored for copper contamination; and (d) determining an amount of copper adsorbed from the aqueous solution by the region of the substrate.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
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Publication number: 20090088984Abstract: A computer system. The computer system including a processor and memory unit coupled to the processor, the memory unit containing instructions that when executed by the processor implement a method for monitoring a solution in a tank used to fabricate integrated circuits, the method comprising the computer implemented steps of: (a) collecting data indicating of an amount of copper in a region of a substrate of a monitor, the monitor comprising an N-type region in a silicon substrate, the region abutting a top surface of the substrate, the monitor having been submerged in the solution for a preset time; (b) comparing the data to a specification for copper content of the solution; (c) if the data indicates a copper content exceeds a limit of the specification for copper, indicating a corrective action is required to prevent copper contamination of the integrated circuits; and (d) repeating steps (a) through (c) periodically.Type: ApplicationFiled: September 28, 2007Publication date: April 2, 2009Inventors: Jay Sanford Burnham, Joseph Kerry Vaughn Comeau, Leslie Peter Crane, James Randall Elliott, Scott Alan Estes, James Spiros Nakos, Eric Jeffrey White
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Publication number: 20090045468Abstract: Trench isolation structure and method of forming trench isolation structures. The structures includes a trench in a silicon region of a substrate, the trench extending from a top surface of the substrate into the silicon region; an ion implantation stopping layer over sidewalls of the trench; a dielectric fill material filling remaining space in the trench, the dielectric fill material not including any materials found in the stopping layer; an N-type dopant species in a first region of the silicon region on a first side of the trench; the N-type dopant species in a first region of the dielectric material adjacent to the first side of the trench; a P-type dopant species in a second region of the silicon region on a second side of the trench; and the P-type dopant species in a second region of the dielectric material adjacent to the second side of the trench.Type: ApplicationFiled: August 16, 2007Publication date: February 19, 2009Inventors: Terence Blackwell Hook, Jeffrey Bowman Johnson, James Spiros Nakos
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Patent number: 7462845Abstract: A method of improving the performance of a charged beam apparatus. The method including: providing a chamber having an interior surface; providing a pump port for evacuating the chamber; providing a substrate holder within the chamber; forming a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and placing one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.Type: GrantFiled: June 5, 2006Date of Patent: December 9, 2008Assignee: International Business Machines CorporationInventors: Alan Michael Chandler, Tushar Desai, Ellis Craig Hayford, Nicholas Mone, Jr., James Spiros Nakos
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Publication number: 20080277597Abstract: An apparatus. The apparatus including: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.Type: ApplicationFiled: July 7, 2008Publication date: November 13, 2008Inventors: Alan Michael Chandler, Tushar Desai, Ellis Craig Hayford, Nicholas Mone, Jr., James Spiros Nakos
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Publication number: 20080258081Abstract: A method of improving the performance of charged beam apparatus. The method including: providing the apparatus, the apparatus comprising: a chamber having an interior surface; a pump port for evacuating the chamber; a substrate holder within the chamber; and a charged particle beam within the chamber, the charged beam generated by a source and the charged particle beam striking the substrate; and positioning one or more liners in contact with one or more different regions of the interior surface of the chamber, the liners preventing material generated by interaction of the charged beam and the substrate from coating the one or more different regions of the interior surface of the chamber.Type: ApplicationFiled: July 3, 2008Publication date: October 23, 2008Inventors: Alan Michael Chandler, Tushar Desai, Ellis Craig Hayford, Nicholas Mone, James Spiros Nakos
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Publication number: 20080102650Abstract: A method of forming a nitrided silicon oxide layer. The method includes: forming a silicon dioxide layer on a surface of a silicon substrate; performing a rapid thermal nitridation of the silicon dioxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form an initial nitrided silicon oxide layer; and performing a rapid thermal oxidation or anneal of the initial nitrided silicon oxide layer at a temperature of less than or equal to about 900° C. and a pressure greater than about 500 Torr to form a nitrided silicon oxide layer. Also a method of forming a MOSFET with a nitrided silicon oxide dielectric layer.Type: ApplicationFiled: October 30, 2006Publication date: May 1, 2008Inventors: Edward Dennis Adams, Jay Sanford Burnham, Evgeni Gousev, James Spiros Nakos, Heather Elizabeth Preuss, Joseph Francis Shepard
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Patent number: 6522304Abstract: An integrated horn antenna device with an integrated circuit (IC) chip including a metallic horn structure having a wide aperture, a horizontal waveguide with a tapered via that electromagnetically communicates with a vertical waveguide structure to transmit energy to and from an electronic sub-component transceiver device forming part of the IC chip. Another embodiment of the invention comprises a plurality of multiple discrete IC chips having the integrated horn antenna devices incorporated therewith forming a module for data transmissions between these IC chips. Another embodiment of the invention includes additional external waveguide structures such as optical fibers external to the chips, where radiation is aligned between the horn structures and these waveguides. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.Type: GrantFiled: April 11, 2001Date of Patent: February 18, 2003Assignee: International Business Machines CorporationInventors: Arne Watson Ballantine, Daniel Charles Edelstein, James Spiros Nakos, Anthony Kendall Stamper
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Patent number: 6498096Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.Type: GrantFiled: March 8, 2001Date of Patent: December 24, 2002Assignee: International Business Machines CorporationInventors: James Allan Bruce, Jonathan Daniel Chapple-Sokol, Charles W. Koburger, III, Michael James Lercel, Randy William Mann, James Spiros Nakos, John Joseph Pekarik, Kirk David Peterson, Jed Hickory Rankin
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Publication number: 20020149530Abstract: An integrated horn antenna device with an integrated circuit (IC) chip including a metallic horn structure having a wide aperture, a horizontal waveguide with a tapered via that electromagnetically communicates with a vertical waveguide structure to transmit energy to and from an electronic sub-component transceiver device forming part of the IC chip. Another embodiment of the invention comprises a plurality of multiple discrete IC chips having the integrated horn antenna devices incorporated therewith forming a module for data transmissions between these IC chips. Another embodiment of the invention includes additional external waveguide structures such as optical fibers external to the chips, where radiation is aligned between the horn structures and these waveguides. Dual damascene processing is used to fabricate the horn antenna device within the IC chip.Type: ApplicationFiled: April 11, 2001Publication date: October 17, 2002Applicant: International Business Machines CorporationInventors: Arne Watson Ballantine, Daniel Charles Edelstein, James Spiros Nakos, Anthony Kendall Stamper
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Patent number: 6215190Abstract: A borderless contact to diffusion with respect to gate conductor is provided by employing a double insulating film stack as a mask for defining the gate conductor shapes for the entire chip and providing a relatively thin damage preventing layer on exposed conductive layer following defining the gate conductor shapes. In one embodiment, a borderless contact is provided by forming an insulating layer on a substrate, providing a conductive layer on the insulating layer, providing a second insulating layer on the conductive layer, providing a third insulating layer on the second insulating layer, removing preselected portions of the second and third insulating layers, providing a damage preventing layer in those areas where the second and third insulating layers have been removed, removing preselected portions of the third insulating layer, removing the damage preventing layer, removing exposed portions of the conductive layer, and removing now exposed portions of the second insulating layer.Type: GrantFiled: May 12, 1998Date of Patent: April 10, 2001Assignee: International Business Machines CorporationInventors: James Allen Bruce, Jonathan Daniel Chapple-Sokol, Charles W. Koburger, III, Michael James Lercel, Randy William Mann, James Spiros Nakos, John Joseph Prxarik, Kirk David Peterson, Jed Hickory Rankin