Abstract: A method of ion cleaving using microwave radiation is described. The method includes using microwave radiation to induce exfoliation of a semiconductor layer from a donor substrate. The donor substrate may be implanted, bonded to a carrier substrate, and heated via the microwave radiation. The implanted portion of the donor substrate may include increased damage and/or dipoles (relative to non-implanted portions of the donor substrate), which more readily absorb microwave radiation. Consequently, by using microwave radiation, an exfoliation time may be reduced to 12 seconds or less. In addition, a presented method also includes the use of focused ion beam implantation to achieve a pattern-less transfer of a semiconductor layer onto a carrier substrate.

Abstract: An electronic apparatus uses a single crystalline silicon substrate disposed adjacent to a flexible substrate. The electronic apparatus may be a flexible flat panel display, or a flexible printed circuit board. The flexible substrate can be made from polymer, plastic, paper, flexible glass, and stainless steel. The flexible substrate is bonded to the single crystalline substrate using an ion implantation process. The ion implantation process involves the use of a noble gas such as hydrogen, helium, xenon, and krypton. A plurality of semiconductor devices are formed on the single crystalline silicon substrate. The semiconductor devices may be thin film transistors for the flat panel display, or active and passive components for the electronic device.

Abstract: Direct focused ion beam (FIB) mixing is given as a method for patterning of metal silicide structures on a silicon surface. This technique allows the fabrication of submicron structures without the use of resist-based lithography methods. VLSI containing metal silicide connects, interconnects and structures may be prepared by the method. Fast semiconductor devices having good circuit speed and reduced RC time delay including the technologies MEMS, MOSFET, CMOS, pMOS, nMOS and BiCMOS result.

Abstract: The invention provides a novel scheme for performing echo cancellation in the presence of double-talk and near-end channel impulse response changes. In one embodiment of the invention, a non-adaptive main filter is updated with the filtering weights of an adaptive shadow filter if the shadow filter cancels near-end echo in a first signal to a greater extent than the main filter. However, if double-talk is present in the first signal, then the non-adaptive filter is not updated. According to one embodiment of the invention, distinguishing between double-talk and channel impulse response changes is accomplished by maintaining extra taps for the main and shadow filters, in addition to taps employed by the main and shadow filters for echo canceling. The corresponding filtering algorithm weights for the additional taps of the main and shadow filters are compared to detect the onset of double-talk and/or channel impulse response changes.

Abstract: Processing of hydroxylapatite sol-gel films on titanium alloy bone prostheses. A method utilizing non-line-of-sight ion beam implantation and/or rapid thermal processing to provide improved bonding of layers of hydroxylapatite to titanium alloy substrates while encouraging bone ingrowth into the hydroxylapatite layers located away from the substrate, is described for the fabrication of prostheses. The first layer of hydroxylapatite is mixed into the substrate by the ions or rapidly thermally annealed, while subsequent layers are heat treated or densified using ion implantation to form layers of decreasing density and larger crystallization, with the outermost layers being suitable for bone ingrowth.

Abstract: A micrometer scale emitter tip or array is disclosed having precisely located tips and surrounding gates. A silicide on the tips reduces tip work function.

Abstract: The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C.

Abstract: The present invention features a process and a resulting article in which copper-based multilevel interconnects are fabricated. The copper-based multilevel interconnect formed by the inventive process first includes the process step of depositing a pattern of copper lines upon or in an applicable substrate, such as silicon dioxide. The copper lines are approximately one micron thick. The lines are coated with approximately 50 to 100 nm of titanium by sputter deposition, and undergo subsequent annealing at approximately 300.degree. C. to 400.degree. C. in an argon ambient. The titanium and copper layers are annealed to provide a Cu.sub.3 Ti alloy at the copper/titanium junction. The unreacted titanium between the copper features is then stripped away by dry etching with fluorine-based etch. The remaining Cu.sub.3 Ti alloy is subsequently transformed into TiN(O) and copper by a rapid thermal annealing in an NH.sub.3 atmosphere at an approximate temperature of below 650.degree. C.

Abstract: The present invention features low-temperature, self-encapsulated, copper interconnect lines on silicon substrates of Ultra-Large Scale Integration (ULSI) circuits. The interconnect lines are a product of a process that includes the following steps: (a) alloying the copper with titanium in an approximate 10 atomic weight percentage of titanium; (b) depositing a layer of the copper/titanium alloy upon a silicon dioxide/silicon substrate of a ULSI circuit; (c) patterning the copper/titanium layer to form interconnect lines on the substrate; (d) forming a titanium rich surface film on the copper interconnect lines by rapid heating of the copper/titanium interconnect lines at an approximate ramping rate of between 60.degree. and 80.degree. C./minute; and (e) nitriding the titanium rich surface of the interconnect lines in an ammonia atmosphere at low temperatures in an approximate range of between 450.degree. to 650.degree. C.

Abstract: An improved process for preparing selective deposition of conductive metals on disilicide encroachment barriers allows the construction of integrated circuit components wherein the metal/disilicide interface is substantially free of O and/or F contamination. The level of interfacial oxygen and/or fluorine contamination in the selective W deposition on the TiSi.sub.2 was substantially reduced or eliminated by first forming a C49 TiSi.sub.2 phase on a substrate, selectively depositing W on the C49 TiSi.sub.2 phase and thereafter annealing at a (minimum) temperature sufficient to convert the high resistivity phase C49 TiSi.sub.2 to the low resistivity phase C54 TiSi.sub.2.

Abstract: A method is provided for producing a low-defect layer of silicon on a sapphire substrate. A silicon-on-sapphire (SOS) wafer is formed by initially epitaxially depositing silicon on the sapphire substrate to form a monocrystalline layer which is substantially free of lattice defects near its surface, but which exhibits a high defect density near the sapphire substrate. The wafer is subsequently subjected to an ion implantation to form an amorphous region in the silicon near the silicon-sapphire interface. The implanted ions are preferably "channeled" through the silicon layer to insure that the amorphous region will be localized in the imperfect region near the substrate, leaving the upper region of the silicon layer undamaged. During a subsequent high temperature anneal cycle, monocrystalline silicon is regrown from the residual upper regions of the silicon down to the silicon-sapphire interface, producing a silicon layer having a greatly reduced defect density throughout the layer.

Abstract: This invention reduces the weight and bulk of the hiker's backpack by eliminating the sleeping bag as a separate item. This is accomplished by providing insulating walls in the knapsack and providing the knapsack with a foldable insulating extension so that the insulated elongated knapsack can be attached to the bottom end of a parka to provide a continuous enveloping sleeping bag.

Abstract: A solid phase epitaxially grown semi-conductor is described wherein a thin film of a semi-conductor material together with a thin film dopant are transported through a metal film onto a substrate, using a temperature below the eutectic temperature for the material.