Abstract: An apparatus for adjusting a microphone sampling rate, the apparatus including an input to receive an audio signal from a microphone and a front-end processing module. The front-end processing module is to generate a plurality of frames from the audio signal received by the microphone, determine a noise profile using the plurality of frames, and adjust a sampling rate of the microphone based on the determined noise profile.

Abstract: Described is an apparatus which comprises: a first oscillator to generate a first clock signal a second oscillator to generate a second clock signal; a phase frequency detector to detect phase difference between the first and second clock signals, and to generate a phase difference; and an output stage, coupled to a load, to generate a power supply for the load according to the phase difference.

Abstract: Described is an apparatus which comprises: a first power supply node to provide a first power supply, a second power supply node, and a third power supply node; a first transistor which is operable to couple the first and second power supply nodes; and a charge pump circuit to provide a boosted voltage to the third power supply node in one mode, and to recover charge from the second power node in another mode. Described is a memory unit which comprises: a DRAM which is operable to be refreshed; a gated power supply node coupled to the DRAM to provide a gated power supply to the DRAM; and a charge recycling circuit to recover charge from the gated power supply node after the DRAM is refreshed.

Abstract: Voltage regulation of processor sub-domains supplied by a same voltage domain power supply rail. Voltage to certain logic units within the voltage domain may be reduced relative to other logic units of the voltage domain, reducing idle time at high power. In an embodiment, a first voltage-regulated sub-domain includes at least one execution unit (EU) while a second voltage-regulated sub-domain includes at least one texture sampler to provide flexibility in setting the graphics core power-performance point beyond modulating active EU count through power domain (gating) control. In embodiments, a sub-domain voltage is regulated by an on-chip DLDO for fast voltage switching. Clock frequency and sub-domain voltage may be switched faster than the voltage of the voltage domain supply rail, permitting a more finely grained power management that can be responsive to EU workload demand.

Abstract: Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.

Abstract: Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.

Abstract: Described is an apparatus which comprises: a plurality of transistors coupled to an input power supply and to a load; a first comparator with a first node coupled to the load, and a second node coupled to a first reference; a second comparator with a first node coupled to the load, and a second node coupled to a second reference, the second reference being different from the first reference; and a logic unit to receive output of the first comparator and output of the second comparator, the logic unit to turn on or off transistors of the plurality of transistors according to outputs of the first and second comparators.

Abstract: Methods of enabling voice processing with minimal power consumption includes recording time-domain audio signal at a first clock frequency and a first voltage, and performing Fast Fourier Transform (FFT) operations on the time-domain audio signal at a second clock frequency to generate frequency-domain audio signal. The frequency domain audio signal may be enhanced to obtain better signal to noise ratio, through one or multiple filtering and enhancing techniques. The enhanced audio signal may be used to generate the total signal energy and estimate the background noise energy. Decision logic may determine from the signal energy and the background noise, the presence or absence of the human voice. The first clock frequency may be different from the second clock frequency.

Abstract: Described herein are apparatus, method, and system for reducing clock-to-output delay of a sequential logic unit in a processor. The apparatus comprises a sequential unit including: a data path, to receive an input signal, including logic gates to operate on a first power supply level, the data path to generate an output signal; and a clock path including logic gates to operate on a second power supply level, the logic gates of the clock path to sample the input signal using a sampling signal to generate the output signal, wherein the second power supply level is higher than the first power supply level. The apparatus improves (i.e. reduces) setup time of the sequential unit and allows the processor to operate at minimum operating voltage (Vmin) without degrading performance of the sequential unit.

Abstract: Described is an apparatus which comprises: a clamp coupled between a first power supply and a second power supply; and a circuit to operate with the second power supply, wherein the clamp is operable to adjust the second power supply when the apparatus enters a low power mode.

Abstract: Sequential circuits with error-detection are provided. They may, for example, be used to replace traditional master-slave flip-flops, e.g., in critical path circuits to detect and initiate correction of late transitions at the input of the sequential. In some embodiments, such sequentials may comprise a transition detector with a time borrowing latch.

Abstract: An integrated circuit (IC) package is disclosed. The IC package includes a first die; and a second die bonded to the CPU die in a three dimensional packaging layout.

Abstract: Some embodiments include a counter having a first generator to generate signals having different frequencies, and a second generator to generate counter values of the counter. Each of the counter values may be based at least in part on a number of transitions of a respective signal among the signals. Other embodiments are described.

Abstract: Disclosed herein are semiconductor device arrays, such as, Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Arrays (CPLAs) that use high-density Spin Transfer Torque (STT)-based memory elements. STT-based memory elements can either be stand-alone FPGAs/CPLAs, or can be embedded in microprocessors and/or digital signal processing (DSP) system-on-chip (SoC) to provide design flexibility for implementing low power, scalable, secure and reconfigurable hardware architecture. Because the configuration is stored on the FPGA/CPLA die itself, the need for loading the configuration from external storage every time is eliminated when the device is powered on. In addition to instant startup, eliminating configuration I/O traffic results in power savings and possible pin count reduction. Security is greatly improved by eliminating the need to store configuration data in an external memory.

Abstract: The disclosed system and method detect and correct register file read path errors that may occur as a result of reducing or eliminating supply voltage guardbands and/or frequency guardbands for a CPU, thereby increasing overall energy efficiency of the system.

Abstract: Described is an apparatus for self-induced reduction in write minimum supply voltage for a memory element. The apparatus comprises: a memory element having cross-coupled inverters coupled to a first supply node; a power device coupled to the first supply node and a second supply node, the second supply node coupled to power supply; and an access device having a gate terminal coupled to a word-line, a first terminal coupled to the memory element, and a second terminal coupled to a bit-line which is operable to be pre-discharged to a logical low level prior to write operation.

Abstract: An aging monitor circuit that provides a more accurate estimate of aging and/or delay in a circuit and/or circuit path. The aging monitor circuit employs a separate aging path with driving and receiving flip flops (FFs) and a tunable replica circuit (TRC) to enable measurements of single-transition DC-stressed path delay that only propagates through stressed transistors or other circuit element(s). A finite state machine (FSM) in the aging monitor circuit is configured to adjust a frequency of a clock signal output by a digitally controlled oscillator (DCO) in response to an error signal output by the receiving FF. The error signal is generated in response to single transition DC-stressed path delay, and therefore enables the adjustment of the frequency of the clock signal to correspond to an amount or effect of the delay.

Abstract: Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.

Abstract: Embodiments for data dependent boosted (DDB) bit cells that may allow for smaller minimum cell supplies (Vmin) without necessarily having to increase device dimensions are presented.

Abstract: A system may include acquisition of a supply voltage information representing past supply voltages supplied to an electrical component, acquisition of a temperature information representing past temperatures of the electrical component, and control of a performance characteristic of the electrical component based on the supply voltage information and the temperature information. Some embodiments may further include determination of a reliability margin based on the supply voltage information, the temperature information, and on a reliability specification of the electrical component, and change of the performance characteristic based on the reliability margin.