Patents by Inventor Jamshed Jalal

Jamshed Jalal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220327057
    Abstract: An apparatus and method for handling stash requests are described. The apparatus has a processing element with an associated storage structure that is used to store data for access by the processing element, and an interface for coupling the processing element to interconnect circuitry. Stash request handling circuitry is also provided that, in response to a stash request targeting the storage structure being received at the interface from the interconnect circuitry, causes a block of data associated with the stash request to be stored within the storage structure. The stash request identifies a given address that needs translating into a corresponding physical address in memory, and also identifies an address space key. Address translation circuitry is used to convert the given address identified by the stash request into the corresponding physical address by performing an address translation that is dependent on the address space key identified by the stash request.
    Type: Application
    Filed: April 8, 2021
    Publication date: October 13, 2022
    Inventors: Jonathan Curtis BEARD, Jamshed JALAL, Steven Douglas KRUEGER, Klas Magnus BRUCE
  • Publication number: 20220308999
    Abstract: An apparatus comprises snoop filter storage circuitry to store snoop filter entries corresponding to addresses and comprising sharer information. Control circuitry selects which sharers, among a plurality of sharers capable of holding cached data, should be issued with snoop requests corresponding to a target address, based on the sharer information of the snoop filter entry corresponding to the target address. The control circuitry is capable of setting a given snoop filter entry corresponding to a given address to an imprecise encoding in which the sharer information provides an imprecise description of which sharers hold cached data corresponding to the given address, and the given snoop filter entry comprises at least one sharer count value indicative of a number of sharers holding cached data corresponding to said address.
    Type: Application
    Filed: March 29, 2021
    Publication date: September 29, 2022
    Inventors: Joshua Randall, Jamshed Jalal, Tusher P. Ringe, Jesse Garrett Beu
  • Publication number: 20220308997
    Abstract: A data processing network includes request nodes with local memories accessible as a distributed virtual memory (DVM) and coupled by an interconnect fabric. Multiple DVM domains are assigned, each containing a DVM node for handling DVM operation requests from request nodes in the domain. On receipt of a request, a DVM node sends a snoop message to other request nodes in its domain and sends a snoop message to one or more peer DVM nodes in other DVM domains. The DVM node receives snoop responses from the request nodes and from the one or more peer DVM nodes, and send a completion message to the first request node. Each peer DVM node sends snoop messages to the request nodes in its domain, collects snoop responses, and sends a single response to the originating DVM node. In this way, DVM operations are performed in parallel.
    Type: Application
    Filed: March 25, 2021
    Publication date: September 29, 2022
    Applicant: Arm Limited
    Inventors: Kishore Kumar Jagadeesha, Jamshed Jalal, Tushar P Ringe, Mark David Werkheiser, Premkishore Shivakumar, Lauren Elise Guckert
  • Patent number: 11445020
    Abstract: Circuitry comprises a set of data handling nodes comprising: two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory; a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and one or more slave nodes including the main memory; in which: a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the condit
    Type: Grant
    Filed: March 24, 2020
    Date of Patent: September 13, 2022
    Assignee: Arm Limited
    Inventors: Jonathan Curtis Beard, Jamshed Jalal, Curtis Glenn Dunham, Roxana Rusitoru
  • Publication number: 20220283972
    Abstract: An apparatus and method are provided for handling protocol conversion. The apparatus has interconnect circuitry for routing messages between components coupled to the interconnect circuitry in a manner that conforms to a first communication protocol. Protocol conversion circuitry is coupled between the interconnect circuitry and an external communication path, for converting messages between the first communication protocol and a second communication protocol that has a layered architecture comprising multiple layers. The protocol conversion circuitry has a gateway component forming one of the components coupled to the interconnect circuitry, and a controller coupled with the gateway component and used to control connection with the external communication path.
    Type: Application
    Filed: March 2, 2021
    Publication date: September 8, 2022
    Inventors: Ashok Kumar TUMMALA, Jamshed JALAL, Antony John HARRIS, Jeffrey Carl DEFILIPPI, Anitha KONA, Bruce James MATHEWSON
  • Patent number: 11431649
    Abstract: The present disclosure advantageously provides a method and system for allocating shared resources for an interconnect. A request is received at a home node from a request node over an interconnect, where the request represents a beginning of a transaction with a resource in communication with the home node, and the request has a traffic class defined by a user-configurable mapping based on one or more transaction attributes. The traffic class of the request is determined. A resource capability for the traffic class is determined based on user configurable traffic class-based resource capability data. Whether a home node transaction table has an available entry for the request is determined based on the resource capability for the traffic class.
    Type: Grant
    Filed: March 26, 2021
    Date of Patent: August 30, 2022
    Assignee: Arm Limited
    Inventors: Mukesh Patel, Jamshed Jalal, Gurunath Ramagiri, Tushar P Ringe, Mark David Werkheiser
  • Patent number: 11409530
    Abstract: A system, apparatus and method for ordering a sequence of processing transactions. The method includes accessing, from a memory, a program sequence of operations that are to be executed. Instructions are received, some of them having an identifier, or mnemonic, that is used to distinguish those identified operations from other operations that do not have an identifier, or mnemonic. The mnemonic indicates a distribution of the execution of the program sequence of operations. The program sequence of operations is grouped based on the mnemonic such that certain operations are separated from other operations.
    Type: Grant
    Filed: August 16, 2018
    Date of Patent: August 9, 2022
    Assignee: Arm Limited
    Inventors: Curtis Glenn Dunham, Pavel Shamis, Jamshed Jalal, Michael Filippo
  • Publication number: 20220164288
    Abstract: Entries in a cluster-to-caching agent map table of a data processing network identify one or more caching agents in a caching agent cluster. A snoop filter cache stores coherency information that includes coherency status information and a presence vector, where a bit position in the presence vector is associated with a caching agent cluster in the cluster-to-caching agent map table. In response to a data request, a presence vector in the snoop filter cache is accessed to identify a caching agent cluster and the map table is accessed to identify target caching agents for snoop messages. In order to reduce message traffic, snoop message are sent only to the identified targets.
    Type: Application
    Filed: November 24, 2020
    Publication date: May 26, 2022
    Applicant: Arm Limited
    Inventors: Gurunath Ramagiri, Jamshed Jalal, Mark David Werkheiser, Tushar P. Ringe, Mukesh Patel, Sakshi Verma
  • Patent number: 11314648
    Abstract: Data processing apparatus comprises a data access requesting node; data access circuitry to receive a data access request from the data access requesting node and to route the data access request for fulfilment by one or more data storage nodes selected from a group of two or more data storage nodes; and indication circuitry to provide a source indication to the data access requesting node, to indicate an attribute of the one or more data storage nodes which fulfilled the data access request; the data access requesting node being configured to vary its operation in response to the source indication.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: April 26, 2022
    Assignee: Arm Limited
    Inventors: Michael Filippo, Jamshed Jalal, Kias Magnus Bruce, Alex James Waugh, Geoffray Lacourba, Paul Gilbert Meyer, Bruce James Mathewson, Phanindra Kumar Mannava
  • Patent number: 11314675
    Abstract: A data processing system comprises a master node to initiate data transmissions; one or more slave nodes to receive the data transmissions; and a home node to control coherency amongst data stored by the data processing system; in which at least one data transmission from the master node to one of the one or more slave nodes bypasses the home node.
    Type: Grant
    Filed: October 22, 2019
    Date of Patent: April 26, 2022
    Assignee: Arm Limited
    Inventors: Guanghui Geng, Andrew David Tune, Daniel Adam Sara, Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal
  • Patent number: 11269773
    Abstract: Circuitry comprises a set of two or more data handling nodes each having respective storage circuitry to hold data; and a home node to serialise data access operations and to control coherency amongst data held by the one or more data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; in which: a requesting node of the set of data handling nodes is configured to communicate a request to the home node for exclusive access to a given instance of data at a given memory address; and the home node is configured, in response to the request, to communicate information to other data handling nodes of the set of data handling nodes to control handling, by those other data handling nodes, of any further instances of the data at the given memory address which are held by those other data handling nodes.
    Type: Grant
    Filed: October 8, 2019
    Date of Patent: March 8, 2022
    Assignee: Arm Limited
    Inventors: Bruce James Mathewson, Phanindra Kumar Mannava, Jamshed Jalal, Klas Magnus Bruce, Andrew John Turner
  • Patent number: 11256623
    Abstract: Apparatus and a corresponding method of operating a hub device, and a target device, in a coherent interconnect system are presented. A cache pre-population request of a set of coherency protocol transactions in the system is received from a requesting master device specifying at least one data item and the hub device responds by cause a cache pre-population trigger of the set of coherency protocol transactions specifying the at least one data item to be transmitted to a target device. This trigger can cause the target device to request that the specified at least one data item is retrieved and brought into cache. Since the target device can therefore decide whether to respond to the trigger or not, it does not receive cached data unsolicited, simplifying its configuration, whilst still allowing some data to be pre-cached.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: February 22, 2022
    Assignee: ARM LIMITED
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Klas Magnus Bruce, Michael Filippo, Paul Gilbert Meyer, Alex James Waugh, Geoffray Matthieu Lacourba
  • Patent number: 11256646
    Abstract: An apparatus and method are provided for handling ordered transactions. The apparatus has a plurality of completer elements to process transactions, a requester element to issue a sequence of ordered transactions, and an interconnect providing, for each completer element, a communication channel between that completer element and the requester element for transfer of signals between that completer element and the requester element in either direction. A given completer element that is processing a given transaction in the sequence is arranged to issue a response signal to the requester element over its associated communication channel that comprises an ordered channel indication to identify whether the associated communication channel has an ordered channel property. The ordered channel property guarantees that processing of transactions issued by the requester element over the associated communication channel in a given order will be completed by the given completer element in the same given order.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: February 22, 2022
    Assignee: Arm Limited
    Inventors: Tushar P Ringe, Jamshed Jalal, Gurunath Ramagiri, Ashok Kumar Tummala, Mark David Werkheiser
  • Patent number: 11200177
    Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.
    Type: Grant
    Filed: October 19, 2016
    Date of Patent: December 14, 2021
    Assignee: ARM LIMITED
    Inventors: Alex James Waugh, Dimitrios Kaseridis, Klas Magnus Bruce, Michael Filippo, Joseph Michael Pusdesris, Jamshed Jalal
  • Patent number: 11188377
    Abstract: Apparatuses, methods of operating apparatuses, interconnects for connecting apparatuses to one another, and methods of operating the interconnects are disclosed. A master apparatus can issue an individual all-zero-data write transaction specifying a data storage location to the interconnect, which conveys the individual all-zero-data write transaction to a target device which writes all-zero-data at the data storage location. No write data is conveyed with the individual all-zero-data write transaction, so that the individual all-zero-data write transaction may be used to clear the data storage location without adding to congestion of a write data channel in the interconnect.
    Type: Grant
    Filed: October 4, 2019
    Date of Patent: November 30, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Mark David Werkheiser, Phanindra Kumar Mannava, Bruce James Mathewson
  • Patent number: 11159636
    Abstract: A data processing apparatus is provided, which includes receiving circuitry to receive a snoop request in respect of requested data on behalf of a requesting node. The snoop request includes an indication as to whether forwarding is to occur. Transmitting circuitry transmits a response to the snoop request and cache circuitry caches at least one data value. When forwarding is to occur and the at least one data value includes the requested data, the response includes the requested data and the transmitting circuitry transmits the response to the requesting node.
    Type: Grant
    Filed: February 8, 2017
    Date of Patent: October 26, 2021
    Assignee: ARM LIMITED
    Inventors: Phanindra Kumar Mannava, Bruce James Mathewson, Jamshed Jalal, Klas Magnus Bruce
  • Patent number: 11146495
    Abstract: The present disclosure advantageously provides a system and method for protocol layer tunneling for a data processing system. A system includes an interconnect, a request node coupled to the interconnect, and a home node coupled to the interconnect. The request node includes a request node processor, and the home node includes a home node processor. The request node processor is configured to send, to the home node, a sequence of dynamic requests, receive a sequence of retry requests associated with the sequence of dynamic requests, and send a sequence of static requests associated with the sequence of dynamic requests in response to receiving credit grants from the home node. The home node processor is configured to send the sequence of retry requests in response to receiving the sequence of dynamic requests, determine the credit grants, and send the credit grants.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: October 12, 2021
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Jamshed Jalal, Kishore Kumar Jagadeesha
  • Publication number: 20210306414
    Abstract: Circuitry comprises a set of data handling nodes comprising: two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory; a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and one or more slave nodes including the main memory; in which: a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the condit
    Type: Application
    Filed: March 24, 2020
    Publication date: September 30, 2021
    Inventors: Jonathan Curtis BEARD, Jamshed JALAL, Curtis Glenn DUNHAM, Roxana RUSITORU
  • Patent number: 11119961
    Abstract: A method and apparatus for data transfer in a data processing network uses both ordered and optimized write requests. A first write request is received at a first node of the data processing network is directed to a first address and has a first stream identifier. The first node determines if any previous write request with the same first stream identifier is pending. When a previous write request is pending, a request for an ordered write is sent to a Home Node of the data processing network associated with the first address. When no previous write request to the first stream identifier is pending, a request for an optimized write is sent to the Home Node. The Home Node and first node are configured to complete a sequence of ordered write requests before the associated data is made available to other elements of the data processing network.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 14, 2021
    Assignee: Arm Limited
    Inventors: Tushar P. Ringe, Jamshed Jalal, Dimitrios Kaseridis
  • Patent number: 11086802
    Abstract: A technique is provided for routing access requests within an interconnect. An apparatus provides a plurality of requester elements for issuing access requests, and a slave element to be accessed in response to the access requests. An interconnect is used to couple the plurality of requester elements with the slave element, and provides an intermediate element that acts as a point of serialisation to order the access requests issued by the plurality of requester elements via the intermediate element. Communication channels are provided within the interconnect to support communication between each of the requester elements and the intermediate element, and between the intermediate element and the slave element.
    Type: Grant
    Filed: March 16, 2020
    Date of Patent: August 10, 2021
    Assignee: Arm Limited
    Inventors: Jamshed Jalal, Tushar P. Ringe, Mark David Werkheiser, Gurunath Ramagiri