Abstract: Wafer inspection method to perform wafer inspection based on photo map information. The wafer inspection method may include: detecting a sample center location on a wafer; compensating the detected sample center location to a compensated center location based on photo map information; and detecting defective dies included in the wafer based on the compensated center location.

Abstract: Wafer inspection method to perform wafer inspection based on photo map information. The wafer inspection method may include: detecting a sample center location on a wafer; compensating the detected sample center location to a compensated center location based on photo map information; and detecting defective dies included in the wafer based on the compensated center location.

Abstract: Wafer inspection method to perform wafer inspection based on photo map information. The wafer inspection method may include: detecting a sample center location on a wafer; compensating the detected sample center location to a compensated center location based on photo map information; and detecting defective dies included in the wafer based on the compensated center location.

Abstract: Wafer inspection method to perform wafer inspection based on photo map information. The wafer inspection method may include: detecting a sample center location on a wafer; compensating the detected sample center location to a compensated center location based on photo map information; and detecting defective dies included in the wafer based on the compensated center location.

Abstract: A semiconductor device having a fuse includes a first insulating layer that has a predetermined metal wire, a second insulating layer that has a heat blocking layer being positioned over the predetermined metal wire, and an upper layer. The upper layer includes a deposition structure having a fuse metal layer and a wiring metal layer. The fuse metal layer has a fuse pattern that is used as a fuse and is exposed via a fuse window in the upper layer. The fuse pattern is electrically connected to the wiring metal layer. The semiconductor device is designed so that the heat blocking layer is larger than the fuse window and is positioned under the fuse metal layer. The semiconductor device is further constructed with the fuse metal layer being formed on the metal wire, thereby preventing limitations in the layout arrangement or in the fabrication process in order to achieve a high degree of integration. A method of manufacturing the above semiconductor device is also described.

Abstract: A method for manufacturing a bipolar transistor semiconductor device for preventing a degradation phenomenon of the transistor resulting from a reduction of a lateral electric field intensity. This is achieved by grading an emitter junction by way of refilling an emitter window with polycrystalline silicon. The resulting transistor structure overcomes the etch stop barrier by removing layer of oxide disposed below a layer of nitride along the region where formation of removing sidewalls of polycrystalline silicon have been formed. Subsequently, a doping distribution of the laterally graded emitter junction can easily be obtained by refilling the emitter window with the removed oxide layer with polycrystalline silicon. Because the shallowness of the oxide layer can be selectively and easily controlled, a thickness of the sidewalls is chosen which most efficiently raises the lateral electric field intensity of the transistor junction.