Patents by Inventor Janusz Rajski

Janusz Rajski has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11150299
    Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: October 19, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
  • Publication number: 20210156918
    Abstract: A circuit comprises: a bit-flipping signal generation device comprising a storage device and configured to generate a bit-flipping signal based on bit-flipping location information, the storage device configured to store the bit-flipping location information for a first number of bits, the bit-flipping location information obtained through a fault simulation process; a pseudo random test pattern generator configured to generate test patterns based on the bit-flipping signal, the pseudo random test pattern generator comprising a register configured to be a linear finite state machine, the register comprising storage elements and bit-flipping devices, each of the bit-flipping devices coupled to one of the storage elements; and scan chains configured to receive the test patterns, wherein the bit-flipping signal causes one of the bit-flipping devices to invert a bit of the register each time a second number of test patterns is being generated by the pseudo random test pattern generator during a test.
    Type: Application
    Filed: November 17, 2020
    Publication date: May 27, 2021
    Inventors: Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Lukasz Rybak, Jerzy Tyszer
  • Publication number: 20210150112
    Abstract: A circuit comprises: a register configured to be a linear finite state machine and comprising storage elements, injection devices, one or more input channels for injecting variables using the injection devices, and one or more feedback devices; a plurality of phase shifters, each of the plurality of phase shifters configured to receive signals from a unique segment of the register; scan chains, serial inputs of the scan chains configured to receive signals from outputs of the plurality of phase shifters, wherein the one or more input channels are coupled to the injection devices at injection points in the register, each of the injection points being assigned to one of the one or more input channels based on lifespan values for the injection points, the injection points being determined based on one or more predetermined requirements.
    Type: Application
    Filed: October 28, 2020
    Publication date: May 20, 2021
    Inventors: Yu Huang, Janusz Rajski, Mark A. Kassab, Nilanjan Mukherjee, Jeffrey Mayer
  • Patent number: 11010523
    Abstract: One, two, or three test pattern generation and encoding processes are performed for a circuit design to generate compressed test patterns for one or two input channel numbers. The one, two, or three test pattern generation and encoding processes are configured to minimize active input channels for each of the compressed test patterns. A test pattern count for each of a plurality of input channel numbers is determined based on the compressed test patterns for the one or two input channel numbers, a number of active input channels for each of the compressed test patterns, and an assumption of similar input data volumes for different numbers of input channels. The test pattern count information can be employed to determine an optimal number of input channels for a test decompressor.
    Type: Grant
    Filed: April 13, 2020
    Date of Patent: May 18, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Yu Huang, Janusz Rajski, Mark A. Kassab, Wu-Tung Cheng
  • Patent number: 10996273
    Abstract: Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: May 4, 2021
    Assignee: Siemens Industry Software Inc.
    Inventors: Sylwester Milewski, Janusz Rajski, Yu Huang
  • Patent number: 10963612
    Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: March 30, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
  • Patent number: 10955460
    Abstract: Disclosed are representative embodiments of methods, apparatus, and systems for test scheduling and test access in a test compression environment. Clusters of test patterns for testing a plurality of cores in a circuit are formed based on test information that includes compressed test data, corresponding tester channel requirements and correlated cores. The formation of test pattern clusters is followed by tester channel allocation. A best-fit scheme or a balanced-fit scheme may be employed to generate channel allocation information. A test access circuit for dynamic channel allocation can be designed based on the channel allocation information.
    Type: Grant
    Filed: March 16, 2011
    Date of Patent: March 23, 2021
    Assignee: Mentor Graphics Corporation
    Inventors: Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer
  • Publication number: 20210018563
    Abstract: A system for testing a circuit comprises scan chains, a controller, and hold-toggle circuitry. The hold-toggle circuitry is configured to allow, according to a control signal generated by the controller, some scan chains in the scan chains to operate in a full-toggle mode and some other scan chains in the scan chains to operate in a hold-toggle mode when a test pattern is being shifted into the scan chains. The control signal also contains information of a hold-toggle pattern for the scan chains operating in the hold-toggle mode. The hold-toggle pattern repeats multiple times when the test pattern is being shifted into the scan chains.
    Type: Application
    Filed: March 21, 2019
    Publication date: January 21, 2021
    Inventors: Janusz Rajski, Yu Huang, Sylwester Milewski, Jerzy Tyszer
  • Patent number: 10830815
    Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: November 10, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Yu Huang
  • Publication number: 20200327268
    Abstract: A scan cell comprises: a state element and selection and combination circuitry. The selection and combination circuitry comprises first combination circuitry configured to combine a signal from a scan input of the scan cell with a signal from a functional circuit input of the scan cell to generate a first signal, second combination circuitry configured to combine the signal from the functional circuit input of the scan cell with an output signal of the state element to generate a second signal, and selection circuitry configured to select an input signal for the state element from the signal from the scan input of the scan cell, the signal from the functional circuit input of the scan cell, the first signal, and the second signal based on two selection input signals of the scan cell.
    Type: Application
    Filed: April 10, 2020
    Publication date: October 15, 2020
    Inventors: Nilanjan Mukherjee, Jedrzej Solecki, Janusz Rajski
  • Patent number: 10788530
    Abstract: Various aspects of the disclosed technology relate to streaming data to circuit blocks in a circuit. A system for streaming data in a circuit comprises a first network comprising first data channels and first interface devices and a second network comprising second data channels and second interface devices. Each of the first interface devices is coupled to ports of one of circuit blocks in the circuit and configurable to transport a plurality of equal-sized data packets consecutively. Each of the second interface devices is coupled to one of the first interface devices and configurable to transport configuration data to the first interface devices. The configuration data comprise data for determining whether or not a first interface device is activated and data for determining which bit or bits of each of the plurality of data packets to be captured, replaced, or captured and replaced by an activated first interface device.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 29, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10775436
    Abstract: Various aspects of the disclosed technology relate to using data throttling to generate streaming data for streaming networks in circuits. A plurality of equal-sized data packets to be transported consecutively in a network to the plurality of circuit blocks are generated. The number of bits in each of the plurality of equal-sized data packets assigned to a circuit block requiring longest data loading time is equal to the number of input ports of the circuit block, while the number of bits in each of the plurality of data packets assigned to each of the rest of the plurality of circuit blocks is equal to or smaller than the number of input ports of the each of rest of the plurality of circuit blocks, determined based on the longest data loading time and data loading time for the each of rest of the plurality of circuit blocks.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: September 15, 2020
    Assignee: Mentor Graphics Corporation
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10509073
    Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.
    Type: Grant
    Filed: July 31, 2017
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Xijiang Lin, Kun-Han Tsai, Mark Kassab, Chen Wang, Janusz Rajski
  • Patent number: 10509072
    Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.
    Type: Grant
    Filed: January 30, 2018
    Date of Patent: December 17, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Sylwester Milewski, Nilanjan Mukherjee, Jedrzej Solecki, Jerzy Tyszer, Justyna Zawada
  • Patent number: 10476740
    Abstract: Various aspects of the disclosed technology relate to generating streaming data and configuration data for streaming networks in circuits. Configuration information for transporting data in a first network to the plurality of circuit blocks in a circuit is determined based on information of the plurality of circuit blocks, information of the first network, the data, user-provided information, or any combination thereof. Sets of data packets are generated from the data based on the configuration information. Each set of the sets of data packets comprises equal-sized data packets to be transported consecutively in the first network. Configuration data to be transported in a second network in the circuit is also generated based on the configuration information. The configuration data comprises data for configuring first interface devices comprised in the first network.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 12, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10473721
    Abstract: Various aspects of the disclosed technology relate to streaming data for testing identical circuit blocks in a circuit. The system for streaming data comprises a first network for transporting equal-sized data packets consecutively and a second network for configuring interface devices of the first network. Each of the data packets comprises bits of test patterns and bits of good-machine test responses. Comparison bits (pass/fail status bits) of an identical circuit block instance may be unloaded directly or may merge with those from other identical circuit block instances to generate accumulated comparison bits which are unloaded. A sticky pass/fail bit may also be generated for each of the identical circuit block instances.
    Type: Grant
    Filed: March 19, 2018
    Date of Patent: November 12, 2019
    Assignee: MENTOR GRAPHICS CORPORATION
    Inventors: Jean-Francois Cote, Mark A. Kassab, Janusz Rajski
  • Patent number: 10444282
    Abstract: Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.
    Type: Grant
    Filed: October 15, 2015
    Date of Patent: October 15, 2019
    Assignee: Mentor Graphics Corporation
    Inventors: Janusz Rajski, Elham K. Moghaddam, Nilanjan Mukherjee, Jerzy Tyszer, Justyna Zawada
  • Publication number: 20190311290
    Abstract: One or more machine-learning models are trained and employed to predict test coverage and test data volume. Input features for the one or more machine-learning models comprise the test configuration features and the design complexity features. The training data are prepared by performing test pattern generation and circuit design analysis. The design complexity features may comprise testability, X-profiling, clock domains, power domains, design-rule-checking warnings, or any combination thereof.
    Type: Application
    Filed: April 5, 2019
    Publication date: October 10, 2019
    Inventors: Yu Huang, Wu-Tung Cheng, Gaurav Veda, Janusz Rajski
  • Publication number: 20190293713
    Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 26, 2019
    Inventors: Janusz Rajski, Yu Huang
  • Publication number: 20190293717
    Abstract: The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.
    Type: Application
    Filed: March 21, 2019
    Publication date: September 26, 2019
    Inventors: Yu Huang, Janusz Rajski, Sylwester Milewski