Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

Abstract: Various aspects of the disclosed technology relate to streaming data for testing identical circuit blocks in a circuit. The system for streaming data comprises a first network for transporting equal-sized data packets consecutively and a second network for configuring interface devices of the first network. Each of the data packets comprises bits of test patterns and bits of good-machine test responses. Comparison bits (pass/fail status bits) of an identical circuit block instance may be unloaded directly or may merge with those from other identical circuit block instances to generate accumulated comparison bits which are unloaded. A sticky pass/fail bit may also be generated for each of the identical circuit block instances.

Abstract: Various aspects of the disclosed technology relate to generating streaming data and configuration data for streaming networks in circuits. Configuration information for transporting data in a first network to the plurality of circuit blocks in a circuit is determined based on information of the plurality of circuit blocks, information of the first network, the data, user-provided information, or any combination thereof. Sets of data packets are generated from the data based on the configuration information. Each set of the sets of data packets comprises equal-sized data packets to be transported consecutively in the first network. Configuration data to be transported in a second network in the circuit is also generated based on the configuration information. The configuration data comprises data for configuring first interface devices comprised in the first network.

Abstract: Various aspects of the disclosed technology relate to conflict-reducing test point insertion techniques. Locations in a circuit design for inserting test points are determined based on internal signal conflicts caused by detecting multiple faults with a single test pattern. Test points are then inserted at the locations. The internal signal conflicts may comprise horizontal conflicts, vertical conflicts, or both. The test points may comprise control points, observation points, or both.

Abstract: One or more machine-learning models are trained and employed to predict test coverage and test data volume. Input features for the one or more machine-learning models comprise the test configuration features and the design complexity features. The training data are prepared by performing test pattern generation and circuit design analysis. The design complexity features may comprise testability, X-profiling, clock domains, power domains, design-rule-checking warnings, or any combination thereof.

Abstract: Constant-output-value gates and buffer gates are determined for gates in a circuit design based on a hold-toggle pattern. The hold-toggle pattern determines in which shift clock cycles in a segment of consecutive shift clock cycles one or more scan chains receive bits based on corresponding bits of a test pattern or same bits as bits of previous shift clock cycles during a shift operation. Activation probabilities and observation probabilities are then determined for circuit nodes of the circuit design based at least in part on the constant-output-value gates and the buffer gates. Finally, test patterns are generated based on the activation probabilities and the observation probabilities.

Abstract: A first score and a second score for each scan cell are first determined based on numbers of test cubes in a set of test cubes having a specified value of “1” and a specified value of “0” for the each scan cell, respectively. A ranking score for each test cube in the set of test cubes is then determined based on combining the first scores and the second scores corresponding to specified bits of the each test cube in the set of test cubes. Test cubes in the set of test cubes are merged according to a sequence based on the ranking scores in a test pattern generation process.

Abstract: The operational mode information and the hold-toggle pattern for a flexible isometric test compression system may be determined based on the plurality of test cubes generated for a subset of the targeted faults, the predetermined size and toggle rate for the hold-toggle pattern, and the predetermined maximum number of device inputs for full-toggle scan chains. The operational mode information comprising information of the full-toggle scan chains may be determined based on reduced toggle ranges first and the hold-toggle pattern may then be determined using a relaxation method. Alternatively, the hold-toggle pattern and the full-toggle scan chains may be determined incrementally together.

Abstract: Various aspects of the present invention relate to scan chain stitching techniques for test-per-clock. With various implementations of the invention, a plurality of scan cell partitions are generated based on combinational paths between scan cells. Scan cells may be assigned to one or more pairs of scan cell partitions based on combinational paths between the scan cells. Each pair of the scan cell partitions comprises one stimuli partition and one compacting partition. Using the plurality of scan cell partitions generated, scan chains are formed based on at least information of combinational paths between scan cell partitions in the plurality of scan cell partitions. The formed scan chains are to be dynamically divided into three groups during a test, which are configured to operate in a shifting-launching mode, a capturing-compacting-shifting mode and a mission mode, respectively.

Abstract: Various aspects of the disclosed technology relate to techniques of using control test points to enhance hardware security. The design-for-security circuitry reuses control test points, a part of design-for-test circuitry. The design-for-security circuitry comprises: identity verification circuitry; scrambler circuitry coupled; and test point circuitry. The test point circuitry comprises scan cells and logic gates The identify verification circuitry outputs an identity verification result to the scrambler circuitry to enable/disable control test points of the test point circuitry through the logic gates, and the scrambler circuitry outputs logic bits for loading the scan cells to activate/inactivate the control test points through the logic gates.

Abstract: A method for applying test patterns to scan chains in a circuit-under-test. The method includes providing a compressed test pattern of bits; decompressing the compressed test pattern into a decompressed test pattern of bits as the compressed test pattern is being provided; and applying the decompressed test pattern to scan chains of the circuit-under-test. The actions of providing the compressed test pattern, decompressing the compressed test pattern, and applying the decompressed pattern are performed synchronously at the same or different clock rates, depending on the way in which the decompressed bits are to be generated. A circuit that performs the decompression includes a decompressor such as a linear finite state machine adapted to receive a compressed test pattern of bits. The decompressor decompresses the test pattern into a decompressed test pattern of bits as the compressed test pattern is being received.

Abstract: Aspects of the disclosed technology relate to techniques of test pattern generation based on the cell transition fault model. An assignment for two consecutive clock cycles at inputs of a complex cell in a circuit design is determined based on a gate-level representation of the circuit design. The assignment includes a first transition at one of the inputs which is sensitized by remaining part of the assignment to cause a second transition at an output of the complex cell. A test pattern that generates the assignment at the inputs and propagates a value at the output corresponding to the second clock cycle of the two consecutive clock cycles from the output to an observation point is then derived based on the gate-level representation.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: Aspects of the disclosed technology relate to low power testing. A low power test circuit comprises a test stimulus source, a controller; and a grouping and selection unit. The grouping and selection unit has inputs coupled to the test stimulus source and the controller and has outputs coupled to a plurality of scan chains. The grouping and selection unit is configured to dynamically group scan chains in the plurality of scan chains into a plurality of scan chain groups and to selectively output either original test pattern values generated by the test stimulus source or a constant value to each scan chain group in the plurality of scan chain groups based on control signals received from the controller.

Abstract: Various aspects of the disclosed technology relate to using capture-per-cycle test points to reduce test application time. A scan-based testing system includes a plurality of regular scan chains and one or more capture-per-cycle scan chains on which scan cells capture and compact test responses at predetermined observation points per shift clock cycle.

Abstract: Disclosed herein are exemplary embodiments of a so-called “X-press” test response compactor. Certain embodiments of the disclosed compactor comprise an overdrive section and scan chain selection logic. Certain embodiments of the disclosed technology offer compaction ratios on the order of 1000×. Exemplary embodiments of the disclosed compactor can maintain about the same coverage and about the same diagnostic resolution as that of conventional scan-based test scenarios. Some embodiments of a scan chain selection scheme can significantly reduce or entirely eliminate unknown states occurring in test responses that enter the compactor. Also disclosed herein are embodiments of on-chip comparator circuits and methods for generating control circuitry for masking selection circuits.

Abstract: Built-in self-test techniques for integrated circuits that address the issue of unknown states. Some implementations use a specialized scan chain selector coupled to a time compactor. The presence of the specialized scan chain selector increases the efficiency in masking X states. Also disclosed are: (1) an architecture of a selector that works with multiple scan chains and time compactors, (2) a method for determining and encoding per cycle scan chain selection masks used subsequently to suppress X states, and (3) a method to handle an over-masking phenomenon.

Abstract: Various aspects of the disclosed technology relate to deterministic built-in self-test. A deterministic built-in self-test system comprises: a decompressor configured at least to decompress one of compressed test patterns stored on chip for a predetermined number of times; and a controller configured at least to output a control signal that inverts outputs of the decompressor at one or more scan shift clock cycles based on control data stored on chip, enabling the system to output the predetermined number of test patterns based on the one of compressed test patterns, wherein the one or more scan shift clock cycles are different for each of the predetermined number of test patterns.

Abstract: Various aspects of the disclosed techniques relate to channel sharing techniques for testing circuits having non-identical cores. Compressed test patterns for a plurality of circuit blocks are generated for channel sharing. Each of the plurality of circuit blocks comprises a decompressor configured to decompress the compressed test patterns. Test data input channels are thus shared by the decompressors. Control data input channels are usually not shared by non-identical circuit blocks in the plurality of circuit blocks.

Abstract: Disclosed herein are exemplary methods, apparatus, and systems for performing timing-aware automatic test pattern generation (ATPG) that can be used, for example, to improve the quality of a test set generated for detecting delay defects or holding time defects. In certain embodiments, timing information derived from various sources (e.g. from Standard Delay Format (SDF) files) is integrated into an ATPG tool. The timing information can be used to guide the test generator to detect the faults through certain paths (e.g., paths having a selected length, or range of lengths, such as the longest or shortest paths). To avoid propagating the faults through similar paths repeatedly, a weighted random method can be used to improve the path coverage during test generation. Experimental results show that significant test quality improvement can be achieved when applying embodiments of timing-aware ATPG to industrial designs.