Abstract: A method of making a power module includes providing a base plate defining a topology pattern, providing a power substrate above the base plate, providing at least two power contacts and arranging solder catches in the at least two power contacts, soldering the at least two power contacts to the power substrate utilizing the solder catches, and securing a housing to the power substrate.

Abstract: A method of making a power module includes providing a base plate defining a topology pattern, providing a power substrate above the base plate, providing at least two power contacts and arranging solder catches in the at least two power contacts, soldering the at least two power contacts to the power substrate utilizing the solder catches, and securing a housing to the power substrate.

Abstract: A power module with multiple equalized parallel power paths supporting multiple parallel bare die power devices constructed with low inductance equalized current paths for even current sharing and clean switching events. Wide low profile power contacts provide low inductance, short current paths, and large conductor cross section area provides for massive current carrying. An internal gate & source kelvin interconnection substrate is provided with individual ballast resistors and simple bolted construction. Gate drive connectors are provided on either left or right size of the module. The module is configurable as half bridge, full bridge, common source, and common drain topologies.

Abstract: A power module with multiple equalized parallel power paths supporting multiple parallel bare die power devices constructed with low inductance equalized current paths for even current sharing and clean switching events. Wide low profile power contacts provide low inductance, short current paths, and large conductor cross section area provides for massive current carrying. An internal gate & source kelvin interconnection substrate is provided with individual ballast resistors and simple bolted construction. Gate drive connectors are provided on either left or right size of the module. The module is configurable as half bridge, full bridge, common source, and common drain topologies.

Abstract: A four quadrant power module with lower substrate parallel power paths and upper substrate equidistant clock tree timing utilizing parallel leg construction in a captive fastener power module housing.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace.

Abstract: High temperature gate driving circuits with improved noise resistance and minimized loss are implemented with high temperature components with a reduced size magnetic isolation transformer. Input broad-pulse width modulated signals are converted to offsetting narrow pulses to cross the reduced size magnetic transformer minimizing isolation losses. One embodiment teaches time and voltage offset narrow single pulses that control a set and reset regeneration of the pulse width output on the secondary side of the transformer. Another embodiment teaches multiple concurrent voltage offset pulses to cross the transformer and charge a threshold capacitor for both filtering noise and controlling the pulse width regeneration on the secondary side of the transformer.

Abstract: Provided are a semiconductor device and a method of fabricating the semiconductor device, the semiconductor device including: a source trace, a drain trace, and a gate trace placed on a substrate; a transistor which is placed on the drain trace and includes a source pad and a gate pad; insulating films placed between the drain and source traces and between the drain and gate traces on the substrate so as to cover sidewall surfaces of the transistor; a source spray electrode which is placed on the insulating film between the source and drain traces and connects the source pad of the transistor and the source trace; and a gate spray electrode placed on the insulating film between the gate and drain traces and connects the gate pad of the transistor and the gate trace.