Patents by Inventor Jared Warner Stark, IV

Jared Warner Stark, IV has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11188342
    Abstract: An apparatus and method for a speculative conditional move instruction. A processor comprising: a decoder to decode a first speculative conditional move instruction; a prediction storage to store prediction data related to previously executed speculative conditional move instructions; and execution circuitry to read first prediction data associated with the speculative conditional move instruction and to execute the speculative conditional move instruction either speculatively or non-speculatively based on the first prediction data.
    Type: Grant
    Filed: April 1, 2020
    Date of Patent: November 30, 2021
    Assignee: Intel Corporation
    Inventors: Amjad Aboud, Gadi Haber, Jared Warner Stark, IV
  • Publication number: 20210200550
    Abstract: Disclosed embodiments relate to systems and methods structured to predict a loop exit. In one example, a processor includes a branch prediction unit to determine a loop exit predictor start corresponding to a finite consistent loop, and an instruction decoder queue to: receive an iteration of the finite consistent loop corresponding to a loop exit predictor and an iteration count, replay one or more instructions of the iteration based on the iteration count, and switch to post-loop instructions responsive to a determination that a number of iterations of the finite consistent loop is equal to the iteration count.
    Type: Application
    Filed: December 28, 2019
    Publication date: July 1, 2021
    Inventors: Alexey Yurievich SIVTSOV, Franck SALA, Jared Warner STARK, IV, Lihu RAPPOPORT
  • Patent number: 11029953
    Abstract: Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows.
    Type: Grant
    Filed: June 26, 2019
    Date of Patent: June 8, 2021
    Assignee: Intel Corporation
    Inventors: Michael Mishaeli, Ido Ouziel, Jared Warner Stark, IV
  • Patent number: 10949208
    Abstract: In one embodiment, an apparatus includes a context-based prediction circuit to receive an instruction address for a branch instruction and a plurality of predictions associated with the branch instruction from a global prediction circuit. The context-based prediction circuit may include: a table having a plurality of entries each to store a context prediction value for a corresponding branch instruction; and a control circuit to generate, for the branch instruction, an index value to index into the table, the control circuit to generate the index value based at least in part on at least some of the plurality of predictions associated with the branch instruction and the instruction address for the branch instruction. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 17, 2018
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Saurabh Gupta, Niranjan Soundararajan, Ragavendra Natarajan, Jared Warner Stark, IV, Lihu Rappoport, Sreenivas Subramoney
  • Publication number: 20200409704
    Abstract: Disclosed embodiments relate to the usage of a branch prediction unit in service of performance sensitive microcode flows. In one example, a processor includes a branch prediction unit (BPU) and a pipeline including a fetch stage to fetch an instruction specifying an opcode, an operand, and a loop condition based on the operand, wherein the BPU is to generate a hint reflecting a predicted result of the loop condition, a decode stage to generate either a first or a second micro-operation flow as per the hint, the pipeline to begin executing the generated micro-operation flow; a read stage to read the operand and resolve the loop condition; and execution circuitry to continue the generated micro-operation flow if the prediction was correct, and, otherwise, to flush the pipeline, update the prediction, and switch from the generated micro-operation flow to the other of the first and second micro-operation flows.
    Type: Application
    Filed: June 26, 2019
    Publication date: December 31, 2020
    Applicant: Intel Corporation
    Inventors: Michael MISHAELI, Ido OUZIEL, Jared Warner STARK, IV
  • Publication number: 20200225959
    Abstract: An apparatus and method for a speculative conditional move instruction. A processor comprising: a decoder to decode a first speculative conditional move instruction; a prediction storage to store prediction data related to previously executed speculative conditional move instructions; and execution circuitry to read first prediction data associated with the speculative conditional move instruction and to execute the speculative conditional move instruction either speculatively or non-speculatively based on the first prediction data.
    Type: Application
    Filed: April 1, 2020
    Publication date: July 16, 2020
    Applicant: Intel Corporation
    Inventors: AMJAD ABOUD, GADI HABER, JARED WARNER STARK, IV
  • Publication number: 20200192670
    Abstract: In one embodiment, an apparatus includes a context-based prediction circuit to receive an instruction address for a branch instruction and a plurality of predictions associated with the branch instruction from a global prediction circuit. The context-based prediction circuit may include: a table having a plurality of entries each to store a context prediction value for a corresponding branch instruction; and a control circuit to generate, for the branch instruction, an index value to index into the table, the control circuit to generate the index value based at least in part on at least some of the plurality of predictions associated with the branch instruction and the instruction address for the branch instruction. Other embodiments are described and claimed.
    Type: Application
    Filed: December 17, 2018
    Publication date: June 18, 2020
    Inventors: Saurabh Gupta, Niranjan Soundararajan, Ragavendra Natarajan, Jared Warner Stark, IV, Lihu Rappoport, Sreenivas Subramoney
  • Patent number: 10620961
    Abstract: An apparatus and method for a speculative conditional move instruction. A processor comprising: a decoder to decode a first speculative conditional move instruction; a prediction storage to store prediction data related to previously executed speculative conditional move instructions; and execution circuitry to read first prediction data associated with the speculative conditional move instruction and to execute the speculative conditional move instruction either speculatively or non-speculatively based on the first prediction data.
    Type: Grant
    Filed: March 30, 2018
    Date of Patent: April 14, 2020
    Assignee: Intel Corporation
    Inventors: Amjad Aboud, Gadi Haber, Jared Warner Stark, IV
  • Publication number: 20200081718
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Application
    Filed: November 12, 2019
    Publication date: March 12, 2020
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Patent number: 10579535
    Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.
    Type: Grant
    Filed: December 15, 2017
    Date of Patent: March 3, 2020
    Assignee: Intel Corporation
    Inventors: Lihu Rappoport, Jared Warner Stark, IV, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
  • Patent number: 10521236
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 29, 2018
    Date of Patent: December 31, 2019
    Assignee: Intel Corporation
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Publication number: 20190303163
    Abstract: An apparatus and method for a speculative conditional move instruction. A processor comprising: a decoder to decode a first speculative conditional move instruction; a prediction storage to store prediction data related to previously executed speculative conditional move instructions; and execution circuitry to read first prediction data associated with the speculative conditional move instruction and to execute the speculative conditional move instruction either speculatively or non-speculatively based on the first prediction data.
    Type: Application
    Filed: March 30, 2018
    Publication date: October 3, 2019
    Inventors: AMJAD ABOUD, GADI HABER, JARED Warner STARK, IV
  • Publication number: 20190303162
    Abstract: In an embodiment, a processor includes a branch prediction circuit and a plurality of processing engines. The branch prediction circuit is to: detect a coherence operation associated with a first memory address; identify a first branch instruction associated with the first memory address; and predict a direction for the identified branch instruction based on the detected coherence operation. Other embodiments are described and claimed.
    Type: Application
    Filed: March 29, 2018
    Publication date: October 3, 2019
    Inventors: Christopher Wilkerson, Binh Pham, Patrick Lu, Jared Warner Stark, IV
  • Publication number: 20190188142
    Abstract: A processor includes a processor core and a micro-op cache communicably coupled to the processor core. The micro-op cache includes a micro-op tag array, wherein tag array entries in the micro-op tag array are indexed according to set and way of set-associative cache, and a micro-op data array to store multiple micro-ops. The data array entries in the micro-op data array are indexed according to bank number of a plurality of cache banks and to a set within one cache bank of the plurality of cache banks.
    Type: Application
    Filed: December 15, 2017
    Publication date: June 20, 2019
    Inventors: Lihu RAPPOPORT, Jared Warner Stark iv, Franck Sala, Michael Tal, Gil Shmueli, Adrian Flesler
  • Publication number: 20180349144
    Abstract: In one embodiment, a processor comprises a branch predictor to generate, in association with a program loop, a frozen history vector comprising a snapshot of a branch history vector; track a current iteration of the program loop; and provide a prediction for a branch instruction associated with the program loop, the prediction based on the frozen history vector and the current iteration of the program loop.
    Type: Application
    Filed: June 6, 2017
    Publication date: December 6, 2018
    Applicant: Intel Corporation
    Inventors: Rahul Pal, Ragavendra Natarajan, Niranjan K. Soundararajan, Sreenivas Subramoney, Daniel Deng, Jared Warner Stark, IV, Hong Wang, Ronak Singhal