Patents by Inventor Jasmeet S. Chawla

Jasmeet S. Chawla has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11107908
    Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 31, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Anurag Chaudhry, Dmitri E. Nikonov, Jasmeet S. Chawla, Christopher J. Wiegand, Kanwaljit Singh, Uygar E. Avci, Ian A. Young
  • Patent number: 11069609
    Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.
    Type: Grant
    Filed: November 3, 2017
    Date of Patent: July 20, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Jasmeet S. Chawla, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young, Robert L. Bristol
  • Patent number: 11056593
    Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.
    Type: Grant
    Filed: September 12, 2017
    Date of Patent: July 6, 2021
    Assignee: Intel Corporation
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry, Jasmeet S. Chawla, Ian A Young
  • Patent number: 10971394
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Grant
    Filed: February 25, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
  • Patent number: 10957844
    Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.
    Type: Grant
    Filed: December 23, 2016
    Date of Patent: March 23, 2021
    Assignee: Intel Corporation
    Inventors: Jasmeet S. Chawla, Sasikanth Manipatruni, Robert L. Bristol, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young
  • Publication number: 20200279805
    Abstract: Techniques are disclosed for forming vias for integrated circuit structures. During an additive via formation process, a dielectric material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is desired to have vias, openings are etched in the dielectric material through the removed regions, and the openings are filled with a first via material. This is then repeated for a second via material. During the subtractive via formation process, a first via material is deposited, an etch stop layer is deposited, a checkerboard pattern is deposited on the etch stop layer, regions in the checkerboard pattern are removed where it is not desired to have vias, openings are etched in the first via material through the removed regions. This is then repeated for a second via material.
    Type: Application
    Filed: November 3, 2017
    Publication date: September 3, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth Manipatruni, Jasmeet S. Chawla, Chia-Ching Lin, Dmitri E. Nikonov, Ian A. Young, Robert L. Bristol
  • Patent number: 10707186
    Abstract: Techniques and mechanisms for forming a bond between wafers using a compliant layer. In an embodiment, a layer or layers of one or more compliant materials is provided on a first surface of a first wafer, and the one or more compliant layers are subsequently bonded to a second surface of a second wafer. The bonded wafers are heated to an elevated temperature at which a compliant layer exhibits non-elastic deformations to facilitate relaxation of stresses caused by wafer distortions. In another embodiment, a material of the compliant layer exhibits viscoelastic behavior at room temperature, wherein stress is mitigated by allowing wafer distortion to relax at room temperature.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: July 7, 2020
    Assignee: Intel Corporation
    Inventors: Mauro J. Kobrinsky, Jasmeet S. Chawla, Stefan Meister, Myra McDonnell, Chytra Pawashe, Daniel Pantuso
  • Publication number: 20200152781
    Abstract: Techniques are disclosed for forming semiconductor integrated circuits including one or more of source and drain contacts and gate electrodes comprising crystalline alloys including a transition metal. The crystalline alloys help to reduce contact resistance to the semiconductor devices. In some embodiments of the present disclosure, this reduction in contact resistance is accomplished by aligning the work function of the crystalline alloy with the work function of the source and drain regions such that a Schottky barrier height associated with an interface between the crystalline alloys and the source and drain regions is in a range of 0.3 eV or less.
    Type: Application
    Filed: September 12, 2017
    Publication date: May 14, 2020
    Applicant: INTEL CORPORATION
    Inventors: Sasikanth Manipatruni, Dmitri E. Nikonov, Uygar E. Avci, Christopher J. Wiegand, Anurag Chaudhry, Jasmeet S. Chawla, Ian A. Young
  • Patent number: 10546772
    Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: January 28, 2020
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Richard E. Schenker, Hui Jae Yoo, Kevin L. Lin, Jasmeet S. Chawla, Stephanie A. Bojarski, Satyarth Suri, Colin T. Carver, Sudipto Naskar
  • Patent number: 10497613
    Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.
    Type: Grant
    Filed: April 29, 2015
    Date of Patent: December 3, 2019
    Assignee: INTEL CORPORATION
    Inventors: Jasmeet S. Chawla, Rami Hourani, Mauro J. Kobrinsky, Florian Gstrein, Scott B. Clendenning, Jeanette M. Roberts
  • Publication number: 20190259935
    Abstract: Magneto-electric spin orbital (MESO) structures having functional oxide vias, and method of fabricating magneto-electric spin orbital (MESO) structures having functional oxide vias, are described. In an example, a magneto-electric spin orbital (MESO) device includes a source region and a drain region in or above a substrate. A first via contact is on the source region. A second via contact is on the drain region, the second via contact laterally adjacent to the first via contact. A plurality of alternating ferromagnetic material lines and non-ferromagnetic conductive lines is above the first and second via contacts. A first of the ferromagnetic material lines is on the first via contact, and a second of the ferromagnetic material lines is on the second via contact. A spin orbit coupling (SOC) via is on the first of the ferromagnetic material lines. A functional oxide via is on the second of the ferromagnetic material lines.
    Type: Application
    Filed: December 23, 2016
    Publication date: August 22, 2019
    Inventors: Jasmeet S. CHAWLA, Sasikanth MANIPATRUNI, Robert L. BRISTOL, Chia-Ching LIN, Dmitri E. NIKONOV, Ian A. YOUNG
  • Publication number: 20190189500
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Application
    Filed: February 25, 2019
    Publication date: June 20, 2019
    Inventors: Manish CHANDHOK, Todd R. YOUNKIN, Eungnak HAN, Jasmeet S. CHAWLA, Marie KRYSAK, Hui Jae YOO, Tristan A. TRONIC
  • Publication number: 20190181249
    Abstract: Embodiments herein describe techniques for a semi-conductor device comprising a channel having a first semiconductor material; a source contact coupled to the channel, comprising a first Heusler alloy; and a drain contact coupled to the channel, comprising a second Heusler alloy. The first Heusler alloy is lattice-matched to the first semiconductor material within a first predetermined threshold. A first Schottky barrier between the channel and the source contact, and a second Schottky barrier between the channel and the drain contact are negative, or smaller than another predetermined threshold. The source contact and the drain contact can be applied to a strained silicon transistor, an III-V transistor, a tunnel field-effect transistor, a dichalcogenide (MX2) transistor, and a junctionless nanowire transistor.
    Type: Application
    Filed: July 1, 2016
    Publication date: June 13, 2019
    Inventors: SASIKANTH MANIPATRUNI, ANURAG CHAUDHRY, DMITRI E. NIKONOV, JASMEET S. CHAWLA, CHRISTOPHER J. WIEGAND, KANWALJIT SINGH, UYGAR E. AVCI, IAN A. YOUNG
  • Patent number: 10256141
    Abstract: A first etch stop layer is deposited on a plurality of conductive features on an insulating layer on a substrate. A second etch stop layer is deposited over an air gap between the conductive features. The first etch stop layer is etched to form a via to at least one of the conductive features.
    Type: Grant
    Filed: September 23, 2015
    Date of Patent: April 9, 2019
    Assignee: Intel Corporation
    Inventors: Manish Chandhok, Todd R. Younkin, Eungnak Han, Jasmeet S. Chawla, Marie Krysak, Hui Jae Yoo, Tristan A. Tronic
  • Publication number: 20190074217
    Abstract: A conductive connector for a microelectronic structure may be formed in an opening in a dielectric layer, wherein a ruthenium/aluminum-containing liner is disposed between the dielectric layer and a substantially aluminum-free copper fill material within the opening. The ruthenium/aluminum-containing liner may be formed by depositing a ruthenium-containing liner and migrating aluminum into the ruthenium-containing liner with an annealing process. The aluminum may be presented as a layer formed either before or after the deposition of a copper fill material, or may be presented within a copper/aluminum alloy fill material wherein the annealing process migrates the aluminum out of the copper/aluminum alloy and into the ruthenium-containing liner.
    Type: Application
    Filed: February 25, 2016
    Publication date: March 7, 2019
    Applicant: Intel Corporation
    Inventors: Christopher J. Jezewski, Ramanan V. Chebiam, Jasmeet S. Chawla, Mauro J. Kobrinsky, James S. Clarke
  • Publication number: 20190035677
    Abstract: A plurality of interconnect features are formed in an interconnect layer on a first insulating layer on a substrate. An opening in the first insulating layer is formed through at least one of the interconnect features. A gap fill layer is deposited in the opening.
    Type: Application
    Filed: March 30, 2016
    Publication date: January 31, 2019
    Inventors: Manish CHANDHOK, Richard E. SCHENKER, Hui Jae YOO, Kevin L. LIN, Jasmeet S. CHAWLA, Stephanie A. BOJARSKI, Satyarth SURI, Colin T. CARVER, Sudipto NASKAR
  • Patent number: 10109583
    Abstract: Embodiments of the invention include an interconnect structure and methods of forming such structures. In an embodiment, the interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. Certain embodiments include one or more first interconnect lines in the ILD and a first dielectric cap positioned above each of the first interconnect lines. For example a surface of the first dielectric cap may contact a top surface of the first hardmask layer. Embodiments may also include one or more second interconnect lines in the ILD arranged in an alternating pattern with the first inter-connect lines. In an embodiment, a second dielectric cap is formed over a top surface of each of the second interconnect lines. For example, a surface of the second dielectric cap contacts a top surface of the first hardmask layer.
    Type: Grant
    Filed: December 24, 2014
    Date of Patent: October 23, 2018
    Assignee: Intel Corporation
    Inventors: Robert L. Bristol, Manish Chandhok, Jasmeet S. Chawla, Florian Gstrein, Eungnak Han, Rami Hourani, Kevin Lin, Richard E. Schenker, Todd R. Younkin
  • Patent number: 10032643
    Abstract: Interconnect structures having alternating dielectric caps and an etchstop liner for semiconductor devices and methods for manufacturing such devices are described. According to an embodiment, an interconnect structure may include an interlayer dielectric (ILD) with a first hardmask layer over a top surface of the ILD. The interconnect structure may also include one or more first interconnect lines in the ILD. A first dielectric cap may be positioned above a top surface of each of the first interconnect lines. Additional embodiments include one or more second interconnect lines in the ILD that are arranged in an alternating pattern with the first interconnect lines. A second dielectric cap may be formed above a top surface of each of the second interconnect lines. Embodiments may also include an etchstop liner that is formed over top surfaces of the first dielectric caps.
    Type: Grant
    Filed: December 22, 2014
    Date of Patent: July 24, 2018
    Assignee: Intel Corporation
    Inventors: Jasmeet S. Chawla, Ruth A. Brain, Richard E. Schenker, Kanwal Jit Singh, Alan M. Myers
  • Publication number: 20180182702
    Abstract: Embodiments of the invention describe low capacitance interconnect structures for semiconductor devices and methods for manufacturing such devices. According to an embodiment of the invention, a low capacitance interconnect structure comprises an interlayer dielectric (ILD). First and second interconnect lines are disposed in the ILD in an alternating pattern. The top surfaces of the first interconnect lines may be recessed below the top surfaces of the second interconnect lines. Increases in the recess of the first interconnect lines decreases the line-to-line capacitance between neighboring interconnects. Further embodiments include utilizing different dielectric materials as etching caps above the first and second interconnect lines. The different materials may have a high selectivity over each other during an etching process. Accordingly, the alignment budget for contacts to individual interconnect lines is increased.
    Type: Application
    Filed: February 23, 2018
    Publication date: June 28, 2018
    Inventors: Christopher J. JEZEWSKI, Jasmeet S. CHAWLA
  • Publication number: 20180082942
    Abstract: A conductive route structure may be formed comprising a conductive trace and a conductive via, wherein the conductive via directly contacts the conductive trace. In one embodiment, the conductive route structure may be formed by forming a dielectric material layer on the conductive trace. A via opening may be formed through the dielectric material layer to expose a portion of the conductive trace and a blocking layer may be from only on the exposed portion of the conductive trace. A barrier line may be formed on sidewalls of the via opening and the blocking layer may thereafter be removed. A conductive via may then be formed within the via opening, wherein the conductive via directly contacts the conductive trace.
    Type: Application
    Filed: April 29, 2015
    Publication date: March 22, 2018
    Applicant: INTEL CORPORATION
    Inventors: Jasmeet S. Chawla, Rami Hourani, Mauro J. Kobrinsky, Florian Gstrein, Scott B. Clendenning, Jeanette M. Roberts