Patents by Inventor Jason A. Gayman

Jason A. Gayman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10452312
    Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: October 22, 2019
    Assignee: INTEL CORPORATION
    Inventors: Zhe Wang, Zeshan A. Chishti, Muthukumar P. Swaminathan, Alaa R. Alameldeen, Kunal A. Khochare, Jason A. Gayman
  • Publication number: 20180188953
    Abstract: Provided are an apparatus, system and method to determine whether to use a low or high read voltage. First level indications of write addresses, for locations in the non-volatile memory to which write requests have been directed, are included in a first level data structure. For a write address of the write addresses having a first level indication in the first level data structure, the first level indication of the write address is removed from the first level data structure and a second level indication for the write address is added to a second level data structure to free space in the first level data structure to indicate a further write address. A first voltage level is used to read data from read addresses mapping to one of the first and second level indications in the first and the second level data structures, respectively.
    Type: Application
    Filed: December 30, 2016
    Publication date: July 5, 2018
    Inventors: Zhe WANG, Zeshan A. CHISHTI, Muthukumar P. SWAMINATHAN, Alaa R. ALAMELDEEN, Kunal A. KHOCHARE, Jason A. GAYMAN
  • Patent number: 9971685
    Abstract: A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set.
    Type: Grant
    Filed: April 1, 2016
    Date of Patent: May 15, 2018
    Assignee: Intel Corporation
    Inventors: Jason A. Gayman, Robert W. Faber
  • Publication number: 20170286293
    Abstract: A first set representing a first plurality of physical block addresses of a non-volatile memory and a second set representing a second plurality of physical block addresses of the non-volatile memory may be identified. In response to a request to perform a wear leveling operation, first data from a first physical block address of the first set may be swapped with second data from a first physical block address of the second set. A second physical block address of the first set that is adjacent to the first physical block address of the first set may be identified. Third data from the second physical block address of the first set may be swapped with fourth data from a second physical block address of the second set that is adjacent to the first physical block of the second set.
    Type: Application
    Filed: April 1, 2016
    Publication date: October 5, 2017
    Inventors: Jason A. Gayman, Robert W. Faber
  • Patent number: 9417684
    Abstract: A mechanism is described for facilitating power governance of non-volatile memory devices using a power governing mechanism employed at a computing device according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a credit pool having a plurality of credits to be released to a plurality of memory channels associated with a plurality of non-volatile memory devices. The plurality of credits may be used to provide sufficient power to perform memory operations associated with a computing device. The method may further include receiving a credit request having a petition to obtain one or more credits for a memory channel of the plurality of memory channels to facilitate performance of a memory operation, determining whether the one or more credits are available in the credit pool, and retrieving the one or more credits from the credit pool, if the one or more credits are available in the credit pool.
    Type: Grant
    Filed: December 22, 2011
    Date of Patent: August 16, 2016
    Assignee: Intel Corporation
    Inventors: Simon D. Ramage, Jason A. Gayman, Joerg Hartung, Curtis A. Gittens, Sowmiya Jayachandran, Richard P. Mangold
  • Publication number: 20130275781
    Abstract: A mechanism is described for facilitating power governance of non-volatile memory devices using a power governing mechanism employed at a computing device according to one embodiment of the invention. A method of embodiments of the invention includes maintaining a credit pool having a plurality of credits to be released to a plurality of memory channels associated with a plurality of non-volatile memory devices. The plurality of credits may be used to provide sufficient power to perform memory operations associated with a computing device. The method may further include receiving a credit request having a petition to obtain one or more credits for a memory channel of the plurality of memory channels to facilitate performance of a memory operation, determining whether the one or more credits are available in the credit pool, and retrieving the one or more credits from the credit pool, if the one or more credits are available in the credit pool.
    Type: Application
    Filed: December 22, 2011
    Publication date: October 17, 2013
    Applicant: Intel Corporation
    Inventors: Simon D. Ramage, Jason A. Gayman, Joerg Hartung, Curtis A. Gittens, Richard P. Mangold
  • Patent number: 7018095
    Abstract: A circuit for sensing on-die temperature at multiple locations using a minimum number of pins is described. Thermal diodes coupled to pins are placed on a die to measure the temperature at various die locations. Voltage is applied to the pins to determine the temperature at each given diode location. The polarity of the voltage applied across the pins determines what diodes are selected for measurement.
    Type: Grant
    Filed: June 27, 2002
    Date of Patent: March 28, 2006
    Assignee: Intel Corporation
    Inventors: Dean J. Grannes, Harjinder Singh, Jason A. Gayman
  • Patent number: 6903559
    Abstract: A system may include a first diode and a device coupled to the first diode. The device may be adapted to transmit a first current through the first diode, to determine a first voltage across the first diode, the first voltage associated with the first current, to transmit a second current through the first diode, and to determine a second voltage across the first diode, the second voltage associated with the second current. The device may be further adapted to transmit a third current through the first diode, to determine a third voltage across the first diode, the third voltage associated with the third current, and to determine a temperature of the first diode based at least in part on the first voltage, the second voltage and the third voltage.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 7, 2005
    Assignee: Intel Corporation
    Inventor: Jason A. Gayman
  • Publication number: 20050073326
    Abstract: A system may include a first diode and a device coupled to the first diode. The device may be adapted to transmit a first current through the first diode, to determine a first voltage across the first diode, the first voltage associated with the first current, to transmit a second current through the first diode, and to determine a second voltage across the first diode, the second voltage associated with the second current. The device may be further adapted to transmit a third current through the first diode, to determine a third voltage across the first diode, the third voltage associated with the third current, and to determine a temperature of the first diode based at least in part on the first voltage, the second voltage and the third voltage.
    Type: Application
    Filed: October 6, 2003
    Publication date: April 7, 2005
    Inventor: Jason Gayman
  • Publication number: 20040001527
    Abstract: A circuit for sensing on-die temperature at multiple locations using a minimum number of pins is described. Thermal diodes coupled to pins are placed on a die to measure the temperature at various die locations. Voltage is applied to the pins to determine the temperature at each given diode location. The polarity of the voltage applied across the pins determines what diodes are selected for measurement.
    Type: Application
    Filed: June 27, 2002
    Publication date: January 1, 2004
    Inventors: Dean J. Grannes, Harjinder Singh, Jason A. Gayman
  • Patent number: 6256673
    Abstract: A client/server network system is disclosed for cyclic multicasting of an image file from a central data provider (server) to one or more remote client machines (workstations) over a computer network with minimum network transmission while allowing any number of client machines (workstations) to download the image file at any moment in time without the need to synchronize with the central server's transmission. The network system includes a computer network; a plurality of remote client machines on the computer network; and a central server for providing a cyclic multicasting of an image file to one or more client machines over the computer network concurrently through the use of different transmission cycles of a single cyclic multicast session.
    Type: Grant
    Filed: December 17, 1998
    Date of Patent: July 3, 2001
    Assignee: Intel Corp.
    Inventor: Jason A. Gayman