Patents by Inventor Jason A. Janesky

Jason A. Janesky has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190214070
    Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
    Type: Application
    Filed: March 19, 2019
    Publication date: July 11, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Jason JANESKY, Syed M. ALAM, Dimitri HOUSSAMEDDINE, Mark DEHERREA
  • Publication number: 20190157550
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Application
    Filed: January 24, 2019
    Publication date: May 23, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Sanjeev AGGARWAL, Kerry NAGEL, Jason Janesky
  • Publication number: 20190123266
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Application
    Filed: December 19, 2018
    Publication date: April 25, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Srinivas V. PIETAMBARAM, Bengt J. AKERMAN, Renu WHIG, Jason A. JANESKY, Nicholas D. RIZZO, Jon M. SLAUGHTER
  • Publication number: 20190115060
    Abstract: Spin-orbit-torque (SOT) control strip lines are provided along the sides of free layers in perpendicular magnetic tunnel junction devices. Current flowing through such SOT control strip lines injects spin current into the free layers such that spin torque is applied to the free layers. The spin torque can be used to force the magnetic state of the free layer to a particular state based on the direction of the current through the SOT control strip line. In other embodiments, the SOT provides an assist to spin-transfer torque generated by current flowing vertically through the magnetic tunnel junction. Some embodiments have dedicated strip lines for a single magnetic tunnel junction such that a three-terminal device results.
    Type: Application
    Filed: October 11, 2018
    Publication date: April 18, 2019
    Applicant: Everspin Technologies, Inc.
    Inventors: Sarin DESHPANDE, Sanjeev AGGARWAL, Jason JANESKY, Jon SLAUGHTER, Phillip LOPRESTI
  • Patent number: 10262713
    Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
    Type: Grant
    Filed: January 9, 2017
    Date of Patent: April 16, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Jason Janesky, Syed M. Alam, Dimitri Houssameddine, Mark Deherrera
  • Patent number: 10230046
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Grant
    Filed: December 28, 2017
    Date of Patent: March 12, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 10199571
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Grant
    Filed: October 2, 2017
    Date of Patent: February 5, 2019
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Publication number: 20180205005
    Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.
    Type: Application
    Filed: March 16, 2018
    Publication date: July 19, 2018
    Applicant: Everspin Technologies, Inc.
    Inventors: Wenchin LIN, Jason JANESKY
  • Publication number: 20180123032
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes. For example, an exemplary method of manufacturing a magnetoresistive device includes etching through a second electrode, second dielectric layer and free magnetic layer to provide a sidewall of (i) an unpinned synthetic antiferromagnetic structure, (ii) a second dielectric layer and (iii) a free magnetic layer; thereafter, forming an encapsulation material on the sidewall of the unpinned synthetic antiferromagnetic structure, second dielectric layer and free magnetic layer, and after forming the encapsulation material, etching through a first dielectric layer.
    Type: Application
    Filed: December 28, 2017
    Publication date: May 3, 2018
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9954163
    Abstract: Structures and methods are disclosed for shielding magnetically sensitive components. One structure includes a substrate, a bottom shield deposited on the substrate, a magnetoresistive semiconductor device having a first surface and a second surface opposing the first surface, the first surface of the magnetoresistive semiconductor device deposited on the bottom shield, a top shield deposited on the second surface of the magnetoresistive semiconductor device, the top shield having a window for accessing the magnetoresistive semiconductor device, and a plurality of interconnects that connect the magnetoresistive semiconductor device to a plurality of conductive elements.
    Type: Grant
    Filed: May 14, 2015
    Date of Patent: April 24, 2018
    Assignee: EVERSPIN TECHNOLOGIES, INC.
    Inventors: Wenchin Lin, Jason Janesky
  • Patent number: 9893275
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Grant
    Filed: January 2, 2017
    Date of Patent: February 13, 2018
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20180026180
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Application
    Filed: October 2, 2017
    Publication date: January 25, 2018
    Applicant: Everspin Technologies, Inc.
    Inventors: Srinivas V. PIETAMBARAM, Bengt J. AKERMAN, Renu WHIG, Jason A. JANESKY, Nicholas D. RIZZO, Jon M. SLAUGHTER
  • Patent number: 9793468
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: October 17, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Publication number: 20170148980
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least one encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Application
    Filed: January 2, 2017
    Publication date: May 25, 2017
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Publication number: 20170117029
    Abstract: Techniques and circuits for testing and configuring bias voltage or bias current for write operations in memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation.
    Type: Application
    Filed: January 9, 2017
    Publication date: April 27, 2017
    Inventors: Jason Janesky, Syed M. Alam, Dimitri Houssameddine, Mark Deherrera
  • Patent number: 9548442
    Abstract: A magnetoresistive structure having two dielectric layers, and method of manufacturing same, includes a free magnetic layer positioned between the two dielectric layers. The method of manufacture comprises at least two etch processes and at least an encapsulation process interposed therebetween wherein the encapsulation is formed on sidewalls of the partially formed magnetoresistive stack between etch processes.
    Type: Grant
    Filed: July 12, 2015
    Date of Patent: January 17, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Sanjeev Aggarwal, Kerry Nagel, Jason Janesky
  • Patent number: 9543041
    Abstract: Techniques and circuits for testing and configuring magnetic memory devices are presented. Registers and nonvolatile storage is included on the memory devices for storing values used to control testing of the memory devices as well as for configuring parameters related to both testing and normal operation. Examples include adjustment of bias voltages, sense amplifier offset values, and timing parameters to improve the efficiency of testing operations as well as improve reliability and speed of normal operation.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: January 10, 2017
    Assignee: Everspin Technologies, Inc.
    Inventors: Jason Janesky, Syed M. Alam, Dimitri Houssameddine, Mark Deherrera
  • Publication number: 20160315252
    Abstract: A magnetoresistive magnetic tunnel junction (MTJ) stack includes a free magnetic region, a fixed magnetic region, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, including cobalt, (ii) a multi-layer region including a plurality of layers of ferromagnetic materials, wherein the plurality of layers of ferromagnetic materials include a layer of one or more ferromagnetic materials including cobalt, and (iii) an anti-ferromagnetic coupling layer disposed between the first layer and the multi-layer region. The free magnetic region may include a circular shape, the one or more ferromagnetic materials of the first layer may include cobalt, iron and boron, and the dielectric layer may be disposed on the first layer.
    Type: Application
    Filed: June 30, 2016
    Publication date: October 27, 2016
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter
  • Patent number: 9444037
    Abstract: A magnetoresistive memory array including a plurality of magnetoresistive memory elements wherein each magnetoresistive memory element comprises a free layer including at least one ferromagnetic layer having perpendicular magnetic anisotropy, a fixed layer, and a tunnel barrier, disposed between and in contact with the free and fixed layers. The tunnel barrier includes a first metal-oxide layer, having a thickness between 1 and 10 Angstroms, a second metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed on the first metal-oxide layer, and a third metal-oxide layer, having a thickness between 3 and 6 Angstroms, disposed over the second metal-oxide layer. In one embodiment, the third metal-oxide layer is in contact with the free layer or fixed layer. The tunnel barrier may also include a fourth metal-oxide layer, having a thickness between 1 and 10 Angstroms, disposed between the second and third metal-oxide layers.
    Type: Grant
    Filed: February 15, 2016
    Date of Patent: September 13, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Renu Whig, Jason Janesky, Nicholas Rizzo, Jon Slaughter, Dimitri Houssameddine
  • Patent number: 9391264
    Abstract: An MRAM bit includes a free magnetic region, a fixed magnetic region comprising an anti-ferromagnetic material, and a dielectric layer positioned between the free magnetic region and the fixed magnetic region. In one aspect, the fixed magnetic region consists essentially of an unpinned, fixed synthetic anti-ferromagnetic (SAF) structure which comprises (i) a first layer of one or more ferromagnetic materials, wherein the one or more ferromagnetic materials includes cobalt, (ii) a second layer of one or more ferromagnetic materials wherein the one or more ferromagnetic materials includes cobalt, (iii) a third layer of one or more ferromagnetic materials, and an anti-ferromagnetic coupling layer, wherein: (a) the anti-ferromagnetic coupling layer is disposed between the first and third layers, and (b) the second layer is disposed between the first layer and the anti-ferromagnetic coupling layer.
    Type: Grant
    Filed: June 2, 2015
    Date of Patent: July 12, 2016
    Assignee: Everspin Technologies, Inc.
    Inventors: Srinivas V. Pietambaram, Bengt J. Akerman, Renu Whig, Jason A. Janesky, Nicholas D. Rizzo, Jon M. Slaughter