Patents by Inventor Jason J. Mangattur

Jason J. Mangattur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8896147
    Abstract: A low power biasing circuit for powering up split-rail electronic circuits includes an intermediate voltage generator at each pad which is supplied by a temporary supply voltage to generate a temporary intermediate voltage only when a power signal indicates that all external voltage rails are not safe, thereby reducing power consumption.
    Type: Grant
    Filed: December 23, 2011
    Date of Patent: November 25, 2014
    Assignee: ATI Technologies ULC
    Inventors: Jason J. Mangattur, Richard W. Fung, Marcus Ng
  • Patent number: 8618834
    Abstract: A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: December 31, 2013
    Assignee: ATI Technologies ULC
    Inventors: Jason J. Mangattur, Richard Fung, Alan Siu Kei Poon
  • Publication number: 20130162036
    Abstract: A method and apparatus for powering up an integrated circuit having a plurality of power domains each coupled to receive power from one of a plurality of power sources, where each power domain includes an internal power detector which senses the power of a plurality of power domains (VDD1, VDD2, VDD3, . . . , VDDn) and compares them to a reference voltage to generate a combined power good (PG) signal. The PG signal is combined with an external system power ok signal at a plurality of AND gate circuits which are respectively powered by the plurality of power domains, thereby generating a plurality of power status signals (POWER_OK) on the destination power domains.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Jason J. Mangattur, Richard W. Fung, Marcus Ng
  • Publication number: 20130162044
    Abstract: A low power biasing circuit for powering up split-rail electronic circuits includes an intermediate voltage generator at each pad which is supplied by a temporary supply voltage to generate a temporary intermediate voltage only when a power signal indicates that all external voltage rails are not safe, thereby reducing power consumption.
    Type: Application
    Filed: December 23, 2011
    Publication date: June 27, 2013
    Inventors: Jason J. Mangattur, Richard W. Fung, Marcus Ng
  • Publication number: 20130162289
    Abstract: A method and apparatus configures an integrated circuit by determining a multi-bit configuration value on a single node. The multi-bit configuration value is determined by using at least a voltage level at the single node and also by detecting a time to reach a voltage threshold level at the single node, based on a voltage ramp generation circuit. The method and apparatus also includes configuring an operation mode of a circuit in the integrated circuit based on the determined multi-bit configuration value from the single node. Multi-bit configuration values may be obtained on multiple single nodes in an integrated circuit. In one example, a voltage level is employed in addition to a time to reach a voltage threshold level whereas in another example a current level on a single node is utilized in combination with detection of a time to reach a voltage threshold level.
    Type: Application
    Filed: December 21, 2011
    Publication date: June 27, 2013
    Applicant: ATI TECHNOLOGIES ULC
    Inventors: Jason J. Mangattur, Richard Fung, Alan Siu Kei Poon