Abstract: An industrial automation controller includes a housing with a forced convection chamber. First and second fans are releasably connected to the housing and are adapted to induce airflow through the forced convection chamber. The first and second fans are each connected to the housing by respective first and second latch systems that each include a primary latch and a secondary latch. The secondary latch imposes a time delay during removal and replacement of a fan to facilitate hot swapping of the fan with a replacement fan. A make-last/break-first contact system is provided for each fan such that the fan is shutdown in a controlled manner prior to removal of the fan from the housing. The controller monitors internal temperature and fan speed. The controller initiates, logs, and reports fault conditions based upon the monitored temperature and/or fan speed. The controller is shut down if the monitored temperature exceeds a select temperature level.

Abstract: Disclosed approaches for validating initialization vectors determining by a configuration control circuit whether or not an input initialization vector is within a range of valid initialization vectors. In response to determining that the initialization vector is within the range of valid initialization vectors, the configuration control circuit decrypts the ciphertext into plaintext using the input initialization vector and configures a memory circuit with the plaintext. In response to determining that the first initialization vector is outside the range of valid initialization vectors, the configuration control circuit signals that the first initialization vector is invalid.

Abstract: An array of non-volatile memory cells includes rows and columns. A volatile storage circuit provides addressable units of storage. A control circuit reads first type data and second type data from one or more of the rows and multiple ones of the columns of the array of non-volatile memory cells. The control circuit stores the first type data and second type data read from each row in one or more addressable units of storage of the volatile storage. A security circuit reads first data from the one or more of the addressable units of the volatile storage and selects from the first data, the second type data that includes one or more bits of each of the one or more of the addressable units. The security circuit performs an integrity check on the selected second type data, and generates an alert signal that indicates a security violation in response to failure of the integrity check.

Abstract: Disclosed approaches for controlling debug access to an integrated circuit (IC) device include receiving a debug packet by a debug interface circuit of the IC device. The debug interface circuit authenticates the debug packet in response to the debug packet having a command code that specifies enable debug mode or a command code that specifies disable debug mode. In response to the debug packet passing authentication and the command code specifying enable, the debug interface circuit enables debug mode of the IC device. In response to the debug packet passing authentication and the command code specifying disable, the debug interface circuit disables the debug mode of the IC device. In response to the debug packet failing authentication, the debug interface circuit rejects the debug packet.

Abstract: A disclosed circuit arrangement includes a bank of efuse cells, first and second sense amplifiers coupled to input signals representing constant logic-1 and logic-0 values, respectively, a storage circuit, an efuse control circuit, and an efuse security circuit. The efuse control circuit inputs signals from the bank of efuse cells and signals that are output from the first and second sense amplifiers, and stores data representative of values of the signals in the storage circuit. The efuse security reads the data from the storage circuit and generates an alert signal having a state that indicates a security violation in response to data representative of the value of the signal from the first sense amplifier indicating a logic-0 value or data representative of the value of the signal from the second sense amplifier indicating a logic-1 value.

Abstract: Protecting circuit designs can include, in response to receiving a first encrypted public key, generating, using a hash circuit within the integrated circuit, a first hash of the first encrypted public key. The first hash can be compared with a second hash that was previously stored within a non-volatile memory of the integrated circuit. In response to determining that the first hash matches the second hash, the first encrypted public key is decrypted resulting in a first decrypted public key. A determination is made whether received configuration data for the device is authentic using the first decrypted public key.

Abstract: Methods and circuits are disclosed for measuring temperature and/or voltage using ring oscillators. In an example implementation, temperature and/or voltage are determined using an iterative measurements of a ring oscillator. The ring oscillator oscillates with a different voltage-temperature response in each of the first, second and third modes. In each iteration, a first set of indications of frequency are determined for a ring oscillator in a first mode, a second mode, and a third mode. A coarse temperature estimate and a coarse voltage estimate of the ring oscillator are determined based on the indications of frequency measured in a first iteration. A more accurate temperature estimate and a more accurate voltage estimate of the ring oscillator are determined as a function of a second set of indications of frequency measured in a second iteration, the coarse temperature estimate, and the coarse voltage estimate.

Abstract: In one approach for protecting a design, a plurality of implementations of the design are generated. Each implementation includes an identification function. One of the implementations is selected as a current implementation, and the current implementation is installed on one or more electronic systems. For each electronic system, a method determines whether or not the current implementation is an authorized version on the electronic system from an output value of the identification function. If in the current implementation is not an authorized version on the electronic system, a signal is output indicating that the current implementation is not an authorized version on the electronic system. Periodically, another one of the implementations is selected as a new current implementation, and the new current installation is used for installations on one or more electronic systems.

Abstract: One approach for authenticating data includes storing a plurality of combinations of representations of public keys and session key IDs in a non-volatile memory. A payload and accompanying public key, session key ID, and signature of the payload are input. The signature is a function of the payload and a private key of a key pair that includes the accompanying public key and the private key. Authenticity of the payload is determined based on the accompanying public key and session key ID and the combinations stored in the non-volatile memory, and from the signature and the payload. In response to determining that the payload is authentic, the payload is processed, and in response to determining that the payload is not authentic, processing of the payload is disabled.

Abstract: A system generally relating to an SoC, which may be a field programmable SoC (“FPSoC”), is disclosed. In this SoC, dedicated hardware includes a processing unit, a first internal memory, a second internal memory, an authentication engine, and a decryption engine. A storage device is coupled to the SoC. The storage device has access to a boot image. The first internal memory has boot code stored therein. The boot code is for a secure boot of the SoC. The boot code is configured to cause the processing unit to control the secure boot.

Abstract: Approaches for configuring a programmable integrated circuit (IC) are disclosed. Encrypted configuration data is input to the programmable IC, and the encrypted configuration data is stored in configuration memory of the programmable IC. As the encrypted configuration data is input, a determination is made as to whether or not the encrypted configuration data is authentic. In response to the encrypted configuration data being authentic, the encrypted configuration data is read from the configuration memory and decrypted, and the decrypted configuration data is stored back in the configuration memory.

Abstract: A method relating generally to loading a boot image is disclosed. In such a method, a header of a boot image file is read by boot code executed by a system-on-chip. It is determined whether the header read has an authentication certificate. If the header has the authentication certificate, authenticity of the header is verified with the first authentication certificate. It is determined whether the header is encrypted. If the header is encrypted, the header is decrypted.

Abstract: One approach for authenticating data includes storing a plurality of combinations of representations of public keys and session key IDs in a non-volatile memory. A payload and accompanying public key, session key ID, and signature of the payload are input. The signature is a function of the payload and a private key of a key pair that includes the accompanying public key and the private key. Authenticity of the payload is determined based on the accompanying public key and session key ID and the combinations stored in the non-volatile memory, and from the signature and the payload. In response to determining that the payload is authentic, the payload is processed, and in response to determining that the payload is not authentic, processing of the payload is disabled.

Abstract: Approaches for restricting the use of an integrated circuit (IC) are described. In response to receiving an encrypted configuration bitstream, a cryptographic key is retrieved from an internal memory of the IC and the encrypted configuration bitstream is decrypted using the cryptographic key to produce a decrypted configuration bitstream. A first signature value of the decrypted configuration bitstream is calculated. A second signature value is retrieved from a write-once memory of the IC. In response to the first signature value being different from the second signature value, configuration of the IC with the bitstream is prevented. In response to the first signature value being equal to the second signature value, configuration of the IC with the bitstream is permitted.

Abstract: A circuit for enabling communication of cryptographic data in an integrated circuit is disclosed. The circuit comprises a first interface coupled to receive data having a first security level; a second interface coupled to receive data having a second security level; a cryptographic application; and a routing block coupled between the first and second interfaces and the cryptographic application, the routing block comprising configurable logic, wherein the routing block is configurable to selectively route the data having the first security level by way of the first interface and to route data having the second security level by way of the second interface. A method of enabling communication of cryptographic data in an integrated circuit is also disclosed.

Abstract: In one embodiment of the invention, a method is provided for protecting against attacks on security of a programmable integrated circuit (IC). At least a portion of an encrypted bitstream input to the programmable IC is decrypted with a cryptographic key stored in the programmable IC. A number of failures to decrypt the encrypted bitstream is tracked. The tracked number is stored in a memory of the programmable IC that retains the number across on-off power cycles of the programmable IC. In response to the number of failures exceeding a threshold, data that prevents the decryption key from being used for a subsequent decryption of a bitstream is stored in the programmable IC.

Abstract: In one embodiment, a cryptographic device is provided. The cryptographic device includes a persistent memory and a decryption control circuit coupled to the persistent memory. The decryption control circuit is configured to receive an encrypted data stream and decrypt a first portion of the encrypted data stream using a first cryptographic key stored in the persistent memory, the first portion including a second cryptographic key. The decryption circuit is configured to decrypt a second portion of the encrypted data stream using the second cryptographic key, the second portion of the encrypted data stream including payload data.

Abstract: A system and method are provided for verifying implementation of a logic core in a complete bitstream. A logic core bitstream is extracted from the complete bitstream. The logic core bitstream is compared to a reference bitstream of the logic core for a target device. In response to no discrepancy in the comparison of the logic core bitstream and the reference bitstream, a data value is stored indicating that the logic core implementation contained in the complete bitstream is verified.

Abstract: A computer-implemented method of verifying isolation between a plurality of modules of a circuit design to be implemented within an integrated circuit can include identifying a first module and at least a second module of the circuit design for the integrated circuit. One or more circuit attributes indicative of isolation between the first module and the second module can be identified and compared with at least one isolation criterion. An indication of whether the first module is isolated from the second module can be output according to results of the comparison.

Abstract: A circuit for implementing a plurality of circuits on a programmable logic device, the circuit comprising a first circuit implemented on a first portion of the programmable logic device; a second circuit implemented on a second portion of the programmable logic device; and a control circuit coupled to the first circuit and the second circuit, the control circuit providing isolation between the first circuit and the second circuit. While the first circuit and the second circuit may comprise redundant circuits implementing a common function, the circuits may also comprise circuits which must be isolated, such as an encryption circuit and a decryption circuit implementing a cryptographic function. A method for implementing a plurality of circuits on a programmable logic device is also disclosed.