Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

Abstract: The claimed subject matter provides a system and/or a method that facilitates utilizing a resolution enhancement for a circuit feature. A scanning electron microscope component (104, 204, 304, 404) can provide at least one two-dimensional image of the circuit feature. An image analysis engine (106, 206, 306, 406) can analyze the two-dimensional image. An advanced process control (APC) engine (108, 208, 308, 408) can generate at least one instruction for at least one of a feed forward control and a feedback control and a process component (102, 202, 302, 402) can utilize the at least one instruction to minimize an error.

Abstract: A reticle includes a first pattern formed in a first die flash region of the reticle and a second pattern different than the first pattern formed in a second die flash region of the reticle. A method for patterning a wafer having a plurality of die regions defined thereon includes exposing a first die region using a first pattern formed on a reticle during a first exposure, repositioning the reticle, and exposing the first die region using a second pattern formed on the reticle during a second exposure.

Abstract: A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.

Abstract: A method includes specifying a plurality of optical proximity correction metrology sites on a wafer. Metrology data is collected from at least a subset of the metrology sites. Data values are predicted for the subset of the metrology sites using an optical proximity correction design model. The collected metrology data is compared to the predicted data values to generate an optical proximity correction metric. A problem condition associated with the optical proximity correction design model is identified based on the optical proximity correction metric.

Abstract: A method includes generating a layout for an integrated circuit device in accordance with a plurality of layout design rules. A plurality of metrology sites on the layout associated with at least one subset of the layout design rules is identified. A metrology tag associated with each of the metrology sites is generated. At least one metrology recipe for determining a characteristic of the integrated circuit device is generated based on the metrology tags. Metrology data is collected using the at least one metrology recipe. A selected layout design rule in the at least one subset is modified based on the metrology data.

Abstract: A method includes generating a layout for an integrated circuit device. A plurality of metrology sites on the layout is generated. A metrology tag associated with each of the metrology sites is generated. Each metrology tag includes identification data, location data, and metrology context data relating to the associated metrology site. A system includes a data store and a metrology tag unit. The data store is operable to store a plurality of metrology tags. Each metrology tag is associated with a metrology site on a layout for an integrated circuit device and includes identification data, location data, and metrology context data relating to the associated metrology site. The metrology tag unit is operable to access at least a subset of the metrology tags and generate a metrology recipe for measuring characteristics of the integrated circuit device based on the subset of metrology tags.

Abstract: A method includes collecting optical data from an unpatterned region including a first process layer. At least one optical parameter of the first process layer is determined based on the optical data associated with the unpatterned region. Optical data is collected from a patterned region including a second process layer. At least one characteristic of the patterned region is determined based on the optical data associated with the patterned region and the at least one optical parameter.