Abstract: A layered assembly for use in a controlled atmosphere chamber includes a plurality of substrates and an electrically functioning layer embedded between two adjacent substrates of the plurality of substrates, the electrically functioning layer being a material configured to secure the two adjacent substrates together using a solid-state bonding process. An electrical termination area is integral with the electrically functioning layer, and a peripheral sealing band is embedded between and extends around a periphery of internal faces of the two adjacent substrates, the peripheral sealing band being a material configured to secure and seal the two adjacent substrates together using the solid-state bonding process. Dielectric regions are present between the two adjacent substrates and between edge boundaries of the electrically functioning layer, the dielectric regions being sealed between the two adjacent substrates by the peripheral sealing band.

Abstract: Processing circuitry (10) performs processing in one of at least three domains (82, 84, 86, 88). Address translation circuitry (16) translates a virtual address of a memory access performed from a current domain to a physical address in one of a plurality of physical address spaces (61) selected based at least on the current domain. The domains include a root domain (82) for managing switching between other domains. The physical address spaces (61) include a root physical address space associated with the root domain (82), separate from physical address spaces associated with other domains.

Abstract: An immersion cooling system and methods for operating the system are described. The system includes a vessel configured to hold thermally conductive, condensable dielectric fluid; a pressure controller to reduce or increase an interior pressure of the vessel; a computer component to be at least partially submerged within the dielectric fluid; and a fluid circulation system to draw the dielectric fluid from a sump area of the vessel, pass the dielectric fluid through a filter and deliver the dielectric fluid to a bath area of the vessel.

Abstract: A virtual slit cycloidal mass spectrometer and spectrometry methods are disclosed. The spectrometer size-selects particles, which in turn serve as a “virtual slit” for a cycloidal mass analyzer. This virtual slit provides unprecedented resolution in a system that takes up a much smaller physical footprint than was previously achievable. This spectrometer may facilitate field sampling of isotopes, such as uranium isotopes.

Abstract: A method for the joining of ceramic pieces includes applying a layer of titanium on a first ceramic piece and applying a layer of titanium on a second ceramic piece; applying a layer of nickel on each of the layers of titanium on the first ceramic piece and the second ceramic piece; applying a layer of nickel phosphorous to each of the layers of nickel on the first ceramic piece and the second ceramic piece; assembling the first ceramic piece and the second ceramic piece with the layers of titanium, nickel, and nickel phosphorous therebetween; pressing the layer of nickel phosphorous of the first ceramic piece against the layer of nickel phosphorous of the second ceramic piece; heating the first ceramic piece and the second ceramic piece to a joining temperature in a vacuum; and cooling the first ceramic piece and the second ceramic piece. A hermetic seal is formed between the first ceramic piece and the second ceramic piece.

Abstract: An apparatus for automated quoting of a computer model. The apparatus comprises at least a processor and a memory communicatively connected to the at least a processor. The memory instructs the at least a processor to receive a computer model comprises a plurality of model-based definitions, wherein the computer model is representative of the part to be manufactured. The memory then instructs the processor to determine manufacturability of the part to be manufactured as function of the plurality of model-based definitions and a plurality of manufacturing specifications, wherein the plurality of manufacturing specifications is generated using a domain specific language. The memory finally instructs the processor to generate a manufacturing estimate as a function of the manufacturability of the part to be manufactured, wherein the manufacturing estimate is generated using a manufacturing machine learning model.

Abstract: An engine system includes a fuel supply including a diesel fuel injector and a gaseous fuel admission valve; an engine including a cylinder configured to receive the diesel fuel and the gaseous fuel; an engine position sensor; an exhaust gas recirculation (EGR) line for adjusting an EGR flow to the cylinder; an exhaust temperature sensor; an air supply configured to supply air to the cylinder; and a controller configured to cause the engine system to adjust an air-to-fuel equivalence ratio. The adjustment is based on one or more of: a minimum air-to-fuel equivalence ratio; an exhaust temperature as compared to a target exhaust temperature; a fuel substitution; and an injection timing.

Abstract: A machine for dispensing an individual portion of a frozen dessert may include a cartridge cart having walls forming a cavity having a longitudinal central axis and configured to accommodate a cartridge. The cartridge may include a tube having first and second ends, a nozzle disposed at the first end, and a piston disposed between the nozzle and the second end and configured to slidably move along the tube. The individual portion of the frozen dessert may be contained within the tube between the nozzle and the piston. The machine may also include a plunger, a drive source operably coupled to the plunger and configured to drive the plunger along the central axis, and a support configured to support the first end of the cartridge such that actuating the drive source causes the individual portion of frozen dessert to dispense through the nozzle.

Abstract: A pressure relieve valve (PRV) secures to the rotating control device (RCD) in a drilling operation. The PRV located at rig flowline secures to a PRV line, such as PRV piping that bypasses the MPD choke, MPD system, UBD systems, and other flow control device(s). The outlet of the RCD is routed via the pressure relief valve to discharge to a safe contained area. Such discharge relieves overpressure of the wellbore to a contained environment via the rig flowline.

Abstract: A virtual slit cycloidal mass spectrometer and spectrometry methods are disclosed. The spectrometer size-selects particles, which in turn serve as a “virtual slit” for a cycloidal mass analyzer. This virtual slit provides unprecedented resolution in a system that takes up a much smaller physical footprint than was previously achievable. This spectrometer may facilitate field sampling of isotopes, such as uranium isotopes.

Abstract: A method of forming a net shape preform for a high performance ballistic helmet includes preparing one or more full prepreg plies, preparing one or more filler prepreg plies, wherein a shape and orientation of one filler prepreg ply of the one or more filler prepreg plies is different from a shape and orientation of another filler prepreg ply of the one or more filler prepreg plies, layering the one or more full prepreg plies with one or more filler prepreg plies to form a ply stack and deforming a portion of the ply stack while constraining the ply stack by applying in-plane tensional force to the ply stack to form the net-shape preform.

Abstract: An apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.

Abstract: An apparatus has memory management circuitry to control access to a memory system based on access control information defined in table entries of a table structure comprising at least two levels of access control table. Table accessing circuitry accesses the table structure to obtain the access control information corresponding to a target address. For a given access control table at a given level of the table structure other than a starting level, the table accessing circuitry selects a selected table entry of the given access control table corresponding to the target address, based on an offset portion of the target address. A size of the offset portion is selected based on a variable nesting control parameter specified in a table entry of a higher-level access control table at a higher level of the table structure than the given access control table.

Abstract: Apparatuses, methods, and programs for performing a translation of a virtual address of a memory access to a physical address associated with a memory location to be accessed are disclosed. A page table descriptor is accessed when performing the translation, which comprises translation parameters for the translation. The descriptor further comprises an integrity check value, wherein the integrity check value is dependent on the translation parameters.

Abstract: Memory access circuitry enforces ownership rights for memory regions. A given memory region is associated with an owner realm specified from multiple realms, each realm corresponding to a portion of at least one software process executed by processing circuitry. A realm management unit (RMU) is provided to perform realm management operations for managing the realms. The memory access circuitry controls access to a given memory region in dependence on at least one status attribute specifying whether the given memory region is an RMU-private memory region reserved for exclusive access by the RMU.

Abstract: An apparatus for processing data comprises memory access circuitry to enforce ownership rights of a plurality of memory regions within a first memory. The memory access circuitry is responsive to a first export command received from a first export command source to perform a first export operation to encrypt the given owned data to form given encrypted data and to store the given encrypted data in a second memory. The memory access circuitry is responsive to a second export command for the given memory region received from a second export command source while the first export operation is being performed to determine whether said second export command source has higher priority than the first export command source and, when the second export command source has a higher priority, to interrupt the first export operation and to perform a second export operation specified by the second export command.

Abstract: An apparatus has address translation circuitry to translate a target virtual address (VA) specified by a memory access request into a target physical address, first/second translation table address storage circuitry to store first/second translation table addresses; and protected region defining data storage circuitry to store region defining data specifying at least one protected region of virtual address space. In response to the memory access request: when the target VA is in the protected region(s), the address translation circuitry translates the target VA based on address translation data from a first translation table structure identified by the first translation table address. When the target VA is outside the protected region(s), the target VA is translated based on address translation data from a second translation table structure identified by the second translation table address.

Abstract: An apparatus (4) comprises memory access circuitry (12) to control access to data stored in a memory; and memory integrity checking circuitry (20) to verify integrity of data stored in the memory, using an integrity tree (26) in which the association between parent and child nodes is provided by a pointer. This helps to reduce the memory footprint of the tree.

Abstract: Apparatus comprising translation circuitry to perform a translation operation to generate a translated second memory address within a second memory address space as a translation of a first memory address within a first memory address space, in which the translation circuitry is configured to generate the translated second memory address in dependence upon translation information stored at one or more translation information addresses; permission circuitry to perform an operation to detect permission information to indicate, for a given second memory address, whether memory access is permitted to the given second memory address; and access circuitry to allow access to data stored at the given second memory address when the permission information indicates that memory access is permitted to the given second memory address.