Patents by Inventor Jaspal Singh Shah

Jaspal Singh Shah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11176972
    Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
    Type: Grant
    Filed: August 31, 2020
    Date of Patent: November 16, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Sanjeev Kumar Jain, Jaspal Singh Shah
  • Publication number: 20210201989
    Abstract: A memory device includes a memory array that includes one or more rows of memory cells and one or more columns of memory cells. The comparator circuitry is operably connected to at least one column of memory cells in the one or more columns of memory cells. The comparator circuitry includes a precompute circuit and a select circuit operably connected to the outputs of the precompute circuit. The precompute circuit is operable to precompute a comparison operation to produce a first precompute signal and a second precompute signal. The select circuit is operable to receive a first cell data signal from a memory cell in the column of memory cells. Based at least on the first cell data signal, the select circuit selects either the first precompute signal or the second precompute signal to output from the comparator circuitry as a signal read from the memory cell.
    Type: Application
    Filed: October 30, 2020
    Publication date: July 1, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jaspal Singh SHAH, Atul KATOCH
  • Patent number: 10964381
    Abstract: A device is disclosed to include a memory cell, a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage at a first pair of terminals of the memory cell. The second write assist unit provides at a second pair of terminals of the memory cell a second operational voltage different from the first operational voltage. In a write operation of the memory cell, the first write assist unit further generates a voltage difference between the first pair of terminals.
    Type: Grant
    Filed: August 10, 2020
    Date of Patent: March 30, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh Shah
  • Publication number: 20200395052
    Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
    Type: Application
    Filed: August 31, 2020
    Publication date: December 17, 2020
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sanjeev Kumar Jain, Jaspal Singh Shah
  • Publication number: 20200372953
    Abstract: A device is disclosed to include a memory cell, a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage at a first pair of terminals of the memory cell. The second write assist unit provides at a second pair of terminals of the memory cell a second operational voltage different from the first operational voltage. In a write operation of the memory cell, the first write assist unit further generates a voltage difference between the first pair of terminals.
    Type: Application
    Filed: August 10, 2020
    Publication date: November 26, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh SHAH
  • Patent number: 10770136
    Abstract: a device is disclosed to include a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage and a second operational voltage to a memory cell. The second write assist unit provides a third operational voltage and a fourth operational voltage to the memory cell. During a write operation, the first write assist unit further adjusts the first operational voltage or the second operational voltage while the third operational voltage and the fourth operational voltage are at a same voltage level, and the second write assist unit further adjusts the third operational voltage or the fourth operational voltage while the first operational voltage and the second operational voltage are at a same voltage level.
    Type: Grant
    Filed: December 5, 2019
    Date of Patent: September 8, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh Shah
  • Patent number: 10762931
    Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: September 1, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Sanjeev Kumar Jain, Jaspal Singh Shah
  • Publication number: 20200111527
    Abstract: a device is disclosed to include a first write assist unit and a second write assist unit. The first write assist unit provides a first operational voltage and a second operational voltage to a memory cell. The second write assist unit provides a third operational voltage and a fourth operational voltage to the memory cell. During a write operation, the first write assist unit further adjusts the first operational voltage or the second operational voltage while the third operational voltage and the fourth operational voltage are at a same voltage level, and the second write assist unit further adjusts the third operational voltage or the fourth operational voltage while the first operational voltage and the second operational voltage are at a same voltage level.
    Type: Application
    Filed: December 5, 2019
    Publication date: April 9, 2020
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh SHAH
  • Publication number: 20200020361
    Abstract: A memory device includes an array of memory cells, such as SRAM cells, and a plurality of peripheral circuits operably coupled to the memory array. A power control circuit is configured to individually control an application of power to each of the plurality of peripheral circuits and the array of memory cells.
    Type: Application
    Filed: December 11, 2018
    Publication date: January 16, 2020
    Inventors: Sanjeev Kumar Jain, Jaspal Singh Shah
  • Patent number: 10510404
    Abstract: A device including a memory cell is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. During a write operation of the memory cell, the first operational voltage and the second operational voltage are configured at different voltage levels, and the third operational voltage and the fourth operational voltage are configured at the same voltage level.
    Type: Grant
    Filed: April 22, 2019
    Date of Patent: December 17, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh Shah
  • Publication number: 20190252018
    Abstract: A device including a memory cell is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. During a write operation of the memory cell, the first operational voltage and the second operational voltage are configured at different voltage levels, and the third operational voltage and the fourth operational voltage are configured at the same voltage level.
    Type: Application
    Filed: April 22, 2019
    Publication date: August 15, 2019
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh SHAH
  • Patent number: 10269418
    Abstract: A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.
    Type: Grant
    Filed: July 5, 2016
    Date of Patent: April 23, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh Shah
  • Patent number: 10102901
    Abstract: A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of the first operational voltage, the second operational voltage, the third operation voltage, the fourth operation voltage, or a combination thereof, by a bias voltage difference.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: October 16, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh Shah
  • Publication number: 20180061488
    Abstract: A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The first inverter is operated with a first operational voltage and a third operational voltage, and the second inverter is operated with a second operational voltage and a fourth operational voltage. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of the first operational voltage, the second operational voltage, the third operation voltage, the fourth operation voltage, or a combination thereof, by a bias voltage difference.
    Type: Application
    Filed: November 6, 2017
    Publication date: March 1, 2018
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh SHAH
  • Publication number: 20170186482
    Abstract: A device including a memory cell and write assist circuit is disclosed. The memory cell includes a first inverter and a second inverter cross-coupled with the first inverter. The write assist circuit is coupled to the memory cell. During a write operation of the memory cell, the write assist circuit is configured to adjust a voltage level of an operational voltage provided to the first inverter or the second inverter by a bias voltage difference.
    Type: Application
    Filed: July 5, 2016
    Publication date: June 29, 2017
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventor: Jaspal Singh SHAH
  • Patent number: 9542995
    Abstract: Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.
    Type: Grant
    Filed: August 27, 2014
    Date of Patent: January 10, 2017
    Inventors: Manoj Sachdev, Jaspal Singh Shah
  • Publication number: 20160203856
    Abstract: Sense amplifier configurations for memories are described. In these configurations, the differential inputs are boosted proportional to the respective bitline voltage enabling a low-voltage, reliable, faster sense amplifier operation. Disclosed sense amplifiers are also capable of compensating the threshold mismatch between the sensing transistors.
    Type: Application
    Filed: August 27, 2014
    Publication date: July 14, 2016
    Inventors: Manoj Sachdev, Jaspal Singh Shah
  • Patent number: 8488403
    Abstract: An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on sensing nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers, amplifiers, and comparators.
    Type: Grant
    Filed: April 8, 2010
    Date of Patent: July 16, 2013
    Inventors: Manoj Sachdev, Mohammad Sharifkhani, Jaspal Singh Shah, David Rennie
  • Publication number: 20110255359
    Abstract: An offset cancellation scheme for sense amplification is described. The scheme consists of group of transistors which are selectively coupled to high and low voltage levels via multi-phase timing. This results in a voltage level on nodes of interest which are a function of transistor mismatch. The resulting voltage levels act to compensates for the transistor mismatch, thereby improving the reliability of the sense amplifier in the presence of process non-idealities. The offset cancellation scheme is applicable to numerous types of sense amplifiers.
    Type: Application
    Filed: April 8, 2010
    Publication date: October 20, 2011
    Inventors: Manoj Sachdev, Mohammad Sharifkhani, Jaspal Singh Shah, David Rennie