Patents by Inventor Jau-Yuann Yang

Jau-Yuann Yang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5436181
    Abstract: A method of self aligning an emitter contact includes forming a base layer (18) on a portion of a collector layer (16). An interface layer (22) is formed on the base layer (18) such that a portion of the base layer (18) remains exposed. An emitter layer (24) is formed on the collector layer (16), the interface layer (22), and the exposed portion of the base layer (18). An emitter cap layer (26) is formed on the emitter layer (24) over the previously exposed area of the base layer (18). An insulating layer (28) is formed on the interface layer (22). An emitter contact (36) is formed on the emitter cap layer (26) at the previously exposed area of the base layer (18). The insulating layer (28) isolates the emitter contact (36) from the base layer (18) and a subsequently formed base contact (38). The insulating layer (28) ensures isolation between the emitter contact ( 36) and the base contact (38) despite misalignment of the emitter contact (36) during formation.
    Type: Grant
    Filed: April 18, 1994
    Date of Patent: July 25, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5420052
    Abstract: A method of fabricating a semiplanar heterojunction bipolar transistor (10) includes forming a subcollector layer (12) and a collector layer (16) onto a substrate layer (14). A collector implant plug (18) is selectively implanted to connect the subcollector layer (12) to the surface of the heterojunction bipolar transistor (10). A second epitaxial growth process causes a base layer (22), an emitter layer (24), and an emitter cap layer (26) to form on the collector layer (16) and the collector implant plug (18). By this process, the base layer (22) is not exposed to subsequent harmful fabrication steps. A base plug region (28) is selectively implanted to connect the base layer (22) to the surface of the heterojunction bipolar transistor (10). A base contact (32) and an emitter contact (30) are selectively formed within the heterojunction region on the base plug region (28) and the emitter cap layer (26), respectively.
    Type: Grant
    Filed: April 19, 1994
    Date of Patent: May 30, 1995
    Assignee: Texas Instruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5407842
    Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
    Type: Grant
    Filed: June 8, 1994
    Date of Patent: April 18, 1995
    Assignee: Texas Intruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5369042
    Abstract: This is a method of forming a bipolar transistor comprising: forming a subcollector layer, having a doping type and a doping level, on a substrate; forming a first layer, of the same doping type and a lower doping level than the subcollector layer, over the subcollector layer; increasing the doping level of first and second regions of the first layer; forming a second layer, of the same doping type and a lower doping level than the subcollector layer, over the first layer; increasing the doping level of a first region of the second layer which is over the first region of the first layer, whereby the subcollector layer, the first region of the first layer and the first region of the second layer are the collector of the transistor; forming a base layer over the second layer of an opposite doping type than the subcollector layer; and forming an emitter layer of the same doping type as the subcollector layer over the base layer. Other devices and methods are also disclosed.
    Type: Grant
    Filed: March 5, 1993
    Date of Patent: November 29, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Francis J. Morris, Jau-Yuann Yang, Donald L. Plumton, Han-Tzong Yuan
  • Patent number: 5342795
    Abstract: This is a method of forming a vertical transistor device comprising: forming an n-type first drain/source layer 42; patterning a portion of the first drain/source layer 42 to form a channel 44 and a trench; forming a p-type gate structure 46 in the trench; and forming a n-type second drain/source layer 48 over the gate structure 46 and the channel 44; contacting the gate structure 54; forming p-ohmic contact to the gate structure 56; forming n-ohmic source contact 54; and forming n-ohmic drain contact 58. Other devices and methods are also disclosed.
    Type: Grant
    Filed: November 15, 1993
    Date of Patent: August 30, 1994
    Assignee: Texas Instruments Incorporated
    Inventors: Han-Tzong Yuan, Donald L. Plumton, Tae S. Kim, Jau-Yuann Yang
  • Patent number: 5243207
    Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.
    Type: Grant
    Filed: November 30, 1992
    Date of Patent: September 7, 1993
    Assignee: Texas Instruments Incorporated
    Inventors: Donald L. Plumton, Francis J. Morris, Jau-Yuann Yang
  • Patent number: 5223449
    Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may be also be integrated on the substrate.
    Type: Grant
    Filed: April 26, 1991
    Date of Patent: June 29, 1993
    Inventors: Francis J. Morris, Donald L. Plumton, Jau-Yuann Yang, Han-Tzong Yuan
  • Patent number: 5077231
    Abstract: This is a method for fabricating integrated heterojunction bipolar transistors (HBTs) and heterojunction field effect transistors (HFETs) on a substrate. The method comprises: forming a subcollector layer 12 over the substrate 10; forming a collector layer 14 over the subcollector layer; forming a base layer 16 over the collector layer; etching the base layer to form one or more base pedestals 16 over a portion of the collector layer; forming a buffer region 18 in a portion of the collector layer over which one or more HFETs are fabricated; forming one or more channel regions 20,22 over the buffer region; forming a wide bandgap material emitter/gate layer 26 over the base pedestal and the channel region; forming isolation regions 30,32, whereby there is one or more separate HBTs and one or more separate HFETs over the substrate utilizing an epitaxially grown emitter/gate layer to form both an HBT emitter and an HFET gate. Other devices and methods are also disclosed.
    Type: Grant
    Filed: March 15, 1991
    Date of Patent: December 31, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Donald L. Plumton, Francis J. Morris, Jau-Yuann Yang
  • Patent number: 5068756
    Abstract: Integrated circuits and fabrication methods incorporating both NPN (192, 194, 210) and PNP (196, 121, 124) heterojunction bipolar transistors together with N channel (198, 200, 216, 218) and P channel (202, 204, 220, 222) JFETs on a single substrate as illustrated in FIG. 10. MESFETs may also be integrated on the substrate.
    Type: Grant
    Filed: July 18, 1990
    Date of Patent: November 26, 1991
    Assignee: Texas Instruments Incorporated
    Inventors: Francis J. Morris, Donald L. Plumton, Jau-Yuann Yang, Han-Tzong Yuan