Patents by Inventor Jaume Roig-Guitart

Jaume Roig-Guitart has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10418439
    Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
    Type: Grant
    Filed: October 10, 2016
    Date of Patent: September 17, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Peter Moens, Zia Hossain
  • Patent number: 10218350
    Abstract: A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and a switchable element. In one embodiment, a first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and a second current-carrying terminal of the switchable element is coupled to the gate of the second transistor. In another embodiment, the switchable element is coupled to the gate of the first transistor and includes a first selectable terminal of the switchable element coupled to a source of the second transistor, and a second selectable terminal of the switchable element coupled to the gate of the second transistor. In a particular embodiment, the circuit can be a cascode circuit.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: February 26, 2019
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Balaji Padmanabhan, Prasad Venkatraman
  • Publication number: 20180356296
    Abstract: An electronic device can include a temperature sensor. The temperature sensor can include a drain electrode including drain fingers spaced apart from the source fingers; a source electrode including source fingers spaced apart from the drain fingers; and a gate electrode including a runner, gate fingers and a conductive bridge. In an embodiment, the runner includes a first portion and a second portion spaced apart from the first portion, the gate fingers are coupled to the runner and each gate finger is disposed between a pair of the source and drain fingers. The conductive bridge connects at least two gate fingers, wherein the conductive bridge is along a conduction path between the first and second portions of the runner. Designs for the temperature sensor may provide a more accurate temperature measurement reflective of a transistor within the electronic device.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume ROIG-GUITART, Herbert DE VLEESCHOUWER, Gordon M. GRIVNA
  • Patent number: 10147785
    Abstract: In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side.
    Type: Grant
    Filed: January 26, 2017
    Date of Patent: December 4, 2018
    Assignee: Semiconductor Components Industries, LLC
    Inventors: Jaume Roig-Guitart, Filip Bauwens
  • Patent number: 10090380
    Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.
    Type: Grant
    Filed: January 28, 2016
    Date of Patent: October 2, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Ana Villamor, Piet Vanmeerbeek, Jaume Roig-Guitart, Filip Bogman
  • Publication number: 20180212021
    Abstract: In at least some embodiments, a semiconductor device structure comprises a first surface comprising a source and a gate; a second surface comprising a drain; a substrate of a first type, wherein the substrate is in contact with the drain; a first column in contact with the substrate and the first surface of the device, the first column comprising a dielectric material; and a mirroring axis, wherein a centerline of the first column is disposed along the mirroring axis, forming a first device side and a second device side, wherein the first device side mirrors the second device side.
    Type: Application
    Filed: January 26, 2017
    Publication date: July 26, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume ROIG-GUITART, Filip BAUWENS
  • Patent number: 9991776
    Abstract: A method and apparatus for switched mode power supply (SMPS) system includes circuitry configured to produce a voltage output based on an input voltage, the SMPS circuitry includes inductive, capacitive and switching elements configured to generate the voltage output. The switching elements include at least one set of cascode coupled devices, each set of cascode coupled devices including a high electron mobility transistor (HEMT) and one of a diode and a field effect transistor (FET) in a cascode coupling. A controller produces a signal to a gate terminal of the FET of the sets of cascode coupled devices to drive the HEMT switching rate to adjust the output voltage. The circuitry of the SMPS further includes circuitry to couple the substrate of at least one HEMT to a high voltage node of the SMPS system to reduce large voltage spikes or dv/dts.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: June 5, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Filip Bauwens
  • Patent number: 9929261
    Abstract: An electronic device can include a low-side HEMT including a segmented gate electrode; and a high-side HEMT coupled to the low-side HEMT, wherein the low-side and high voltage HEMTs are integrated within a same semiconductor die. In another aspect, an electronic device can include a source electrode; a low-side HEMT; a high-side HEMT coupled to the low-side HEMT; and a resistive element. In an embodiment, the resistive element can be coupled to the source electrode and a gate electrode of the high voltage HEMT, and in another embodiment, the resistive element can be coupled to the source electrode and a drain of the low-side HEMT. A process of forming an electronic device can include forming a channel layer over a substrate; and forming a gate electrode over the channel layer. The gate electrode can be a segmented gate electrode of a HEMT.
    Type: Grant
    Filed: April 7, 2016
    Date of Patent: March 27, 2018
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Jaume Roig-Guitart, Marnix Tack, Johan Camiel Julia Janssens
  • Publication number: 20180026630
    Abstract: A circuit can include a first transistor including a source and a gate; a second transistor including a drain and a gate, wherein the source of the first transistor is coupled to the drain of the second transistor; and a switchable element. In one embodiment, a first current-carrying terminal of the switchable element is coupled to the gate of the first transistor, and a second current-carrying terminal of the switchable element is coupled to the gate of the second transistor. In another embodiment, the switchable element is coupled to the gate of the first transistor and includes a first selectable terminal of the switchable element coupled to a source of the second transistor, and a second selectable terminal of the switchable element coupled to the gate of the second transistor.
    Type: Application
    Filed: July 20, 2016
    Publication date: January 25, 2018
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume ROIG-GUITART, Balaji PADMANABHAN, Prasad VENKATRAMAN
  • Publication number: 20170294530
    Abstract: An electronic device can include a low-side HEMT including a segmented gate electrode; and a high-side HEMT coupled to the low-side HEMT, wherein the low-side and high voltage HEMTs are integrated within a same semiconductor die. In another aspect, an electronic device can include a source electrode; a low-side HEMT; a high-side HEMT coupled to the low-side HEMT; and a resistive element. In an embodiment, the resistive element can be coupled to the source electrode and a gate electrode of the high voltage HEMT, and in another embodiment, the resistive element can be coupled to the source electrode and a drain of the low-side HEMT. A process of forming an electronic device can include forming a channel layer over a substrate; and forming a gate electrode over the channel layer. The gate electrode can be a segmented gate electrode of a HEMT.
    Type: Application
    Filed: April 7, 2016
    Publication date: October 12, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter MOENS, Jaume ROIG-GUITART, Marnix TACK, Johan Camiel Julia JANSSENS
  • Patent number: 9780086
    Abstract: A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.
    Type: Grant
    Filed: September 2, 2015
    Date of Patent: October 3, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig Guitart, Samir Mouhoubi, Filip Bauwens
  • Publication number: 20170179825
    Abstract: A method and apparatus for switched mode power supply (SMPS) system includes circuitry configured to produce a voltage output based on an input voltage, the SMPS circuitry includes inductive, capacitive and switching elements configured to generate the voltage output. The switching elements include at least one set of cascode coupled devices, each set of cascode coupled devices including a high electron mobility transistor (HEMT) and one of a diode and a field effect transistor (FET) in a cascode coupling. A controller produces a signal to a gate terminal of the FET of the sets of cascode coupled devices to drive the HEMT switching rate to adjust the output voltage. The circuitry of the SMPS further includes circuitry to couple the substrate of at least one HEMT to a high voltage node of the SMPS system to reduce large voltage spikes or dv/dts.
    Type: Application
    Filed: April 27, 2016
    Publication date: June 22, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume ROIG-GUITART, Filip BAUWENS
  • Publication number: 20170062411
    Abstract: A semiconductor device includes a semiconductor substrate defining a major surface. The device further includes a first region including at least a first pillar of a first conductivity type extending in a vertical orientation with respect to the major surface. The device further includes a second region of the first conductivity type. The first pillar includes a higher doping concentration than the second region. The device further includes a Schottky contact coupled to the second region.
    Type: Application
    Filed: September 2, 2015
    Publication date: March 2, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume ROIG GUITART, Samir MOUHOUBI, Filip BAUWENS
  • Publication number: 20170033176
    Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
    Type: Application
    Filed: October 10, 2016
    Publication date: February 2, 2017
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume ROIG-GUITART, Peter MOENS, Zia HOSSAIN
  • Patent number: 9543291
    Abstract: In one embodiment, a method of forming a semiconductor device can comprise; forming a HEM device on a semiconductor substrate. The semiconductor substrate provides a current carrying electrode for the semiconductor device and one or more internal conductor structures provide a vertical current path between the semiconductor substrate and regions of the HEM device.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: January 10, 2017
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter Moens, Jaume Roig Guitart
  • Patent number: 9490372
    Abstract: At least one embodiment is directed to a semiconductor edge termination structure, where the edge termination structure comprises several doped layers and a buffer layer.
    Type: Grant
    Filed: September 7, 2011
    Date of Patent: November 8, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig Guitart, Peter Moens, Zia Hossain
  • Patent number: 9412811
    Abstract: In one embodiment, a semiconductor device has a superjunction structure formed adjoining a low-doped n-type region. A low-doped p-type region is formed adjoining the superjunction structure above the low-doped n-type region and is configured to improve Eas characteristics. A body region is formed adjacent the low-doped p-type region and a control electrode structure is formed adjacent the body region for controlling a channel region within the body region.
    Type: Grant
    Filed: November 2, 2015
    Date of Patent: August 9, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig Guitart, Peter Moens, Piet Vanmeerbeek
  • Patent number: 9413348
    Abstract: An electronic device can include a switch coupled to a switching node. In an embodiment, the switch has a breakdown voltage is less than 2.0 times the designed operating voltage. In another embodiment, the electronic device can further include another switch, wherein both switches are coupled to each other at a switching node. The switches can have different breakdown voltages. In a particular embodiment, either or both switches can include a field-effect transistor and a zener diode that are connected in parallel. The zener diode can be designed to breakdown at a relatively lower fraction of the designed operating voltage as compared to a conventional device. Embodiments can be used to reduce voltage overshoot and ringing at the switching node that may occur after changing the states of the first and second switches. Processes of forming the electronic device can be implemented without significant complexity.
    Type: Grant
    Filed: December 19, 2014
    Date of Patent: August 9, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig-Guitart, Filip Bauwens, Chin Foong Tong
  • Publication number: 20160148997
    Abstract: In one embodiment, a semiconductor substrate is provided having a localized superjunction structure extending from a major surface. A doped region is then formed adjacent the localized superjunction structure to create a charge imbalance therein. In one embodiment, the doped region can be an ion implanted region formed within the localized superjunction structure. In another embodiment, the doped region can be an epitaxial layer having a graded dopant profile adjoining the localized superjunction structure. The charge imbalance can improve, among other things, unclamped inductive switching (UIS) performance.
    Type: Application
    Filed: January 28, 2016
    Publication date: May 26, 2016
    Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Peter MOENS, Ana VILLAMOR, Piet VANMEERBEEK, Jaume ROIG-GUITART, Filip BOGMAN
  • Patent number: 9343528
    Abstract: An electronic device can include an electronic component and a termination region adjacent to the electronic component region. In an embodiment, the termination region can include an insulating region that extends a depth into a semiconductor layer, wherein the depth is less than 50% of the thickness of the semiconductor layer. In another embodiment, the termination region can include a first insulating region that extends a first depth into the semiconductor layer, and a second insulating region that extends a second depth into the semiconductor layer, wherein the second depth is less than the first depth. In another aspect, a process of forming an electronic device can include patterning a semiconductor layer to define a trench within termination region while another trench is being formed for an electronic component within an electronic component region.
    Type: Grant
    Filed: April 10, 2014
    Date of Patent: May 17, 2016
    Assignee: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC
    Inventors: Jaume Roig Guitart, Zia Hossain, Peter Moens, Gordon M. Grivna