Patents by Inventor Javier A. Delacruz

Javier A. Delacruz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210225811
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 22, 2021
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Publication number: 20210217858
    Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.
    Type: Application
    Filed: March 30, 2021
    Publication date: July 15, 2021
    Inventors: Javier A. Delacruz, David Edward Fisch
  • Patent number: 11063017
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide an improved data transfer rate of 1 gigabits per second over at least a 6 mm span, for example. The embedded interposers are not limited to use with memory modules.
    Type: Grant
    Filed: August 29, 2019
    Date of Patent: July 13, 2021
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Publication number: 20210202445
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Application
    Filed: November 25, 2020
    Publication date: July 1, 2021
    Inventors: Javier A. DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Publication number: 20210202387
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Application
    Filed: March 15, 2021
    Publication date: July 1, 2021
    Inventors: Ilyas Mohammed, Steven L. Teig, Javier A. Delacruz
  • Publication number: 20210202428
    Abstract: A bonded structure can include a first element having a first conductive interface feature and a second element having a second conductive interface feature. An integrated device can be coupled to or formed with the first element or the second element. The first conductive interface feature can be directly bonded to the second conductive interface feature to define an interface structure. The interface structure can be disposed about the integrated device in an at least partially annular profile to connect the first and second elements.
    Type: Application
    Filed: December 22, 2020
    Publication date: July 1, 2021
    Inventors: Liang Wang, Rajesh Katkar, Javier A. DeLaCruz, Arkalgud R. Sitaram
  • Publication number: 20210193624
    Abstract: A memory structure is provided, including a NAND block comprising a plurality of oxide layers, the plurality of layers forming a staircase structure at a first edge of the NAND block, a plurality of vias disposed on the staircase structure of NAND block, two or more of plurality of vias terminating along a same plane, a plurality of first bonding interconnects disposed on the plurality of vias, a plurality of bitlines extending across the NAND block, and a plurality of second bonding interconnects disposed along the bitlines. The memory structure may be stacked on another of the memory structure to form a stacked memory device.
    Type: Application
    Filed: December 15, 2020
    Publication date: June 24, 2021
    Inventors: Javier A. Delacruz, Belgacem Haba, Rajesh Katkar, Pearl Po-Yee Cheng
  • Publication number: 20210193603
    Abstract: A bonded structure is disclosed. The bonded structure can include a first element that has a first plurality of contact pads. The first plurality of contact pads includes a first contact pad and a second redundant contact pad. The bonded structure can also include a second element directly bonded to the first element without an intervening adhesive. The second element has a second plurality of contact pads. The second plurality of contact pads includes a third contact pad and a fourth redundant contact pad. The first contact pad is configured to connect to the third contact pad. The second contact pad is configured to connect to the fourth contact pad. The bonded structure can include circuitry that has a first state in which an electrical signal is transferred to the first contact pad and a second state in which the electrical signal is transferred to the second contact pad.
    Type: Application
    Filed: December 17, 2020
    Publication date: June 24, 2021
    Inventors: Javier A. DeLACruz, Belgacem Haba, Jung Ko
  • Publication number: 20210175206
    Abstract: An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.
    Type: Application
    Filed: November 20, 2020
    Publication date: June 10, 2021
    Applicant: Xcelsis Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Cyprian Emeka Uzoh, Rajesh Katkar, Ilyas Mohammed
  • Publication number: 20210166995
    Abstract: Hard IP blocks, such as SerDes chips, are designed with keepout zones beneath the surface interconnects, the keepout zones being spaces within the chip where there is no circuitry. Connections can be formed between surface interconnects on an under surface of the SerDes chip that faces the host die, and surface interconnects on an upper surface of the SerDes chip that interfaces without external devices. Accordingly, redistribution layers routing around an outer periphery of the SerDes chip are no longer needed, and the resistive capacitive load remains low so as not to adversely impact transmitted signals.
    Type: Application
    Filed: February 10, 2021
    Publication date: June 3, 2021
    Inventor: Javier A. Delacruz
  • Patent number: 11024220
    Abstract: Apparatus and method relating generally to an LED display is disclosed. In such an apparatus, a driver die has a plurality of driver circuits. A plurality of light-emitting diodes, each having a thickness of 10 microns or less and discrete with respect to one another, are respectively interconnected to the plurality of driver circuits. The plurality of light-emitting diodes includes a first portion for a first color, a second portion for a second color, and a third portion for a third color respectively obtained from a first, a second, and a third optical wafer. The first, the second, and the third color are different from one another.
    Type: Grant
    Filed: May 31, 2018
    Date of Patent: June 1, 2021
    Assignee: Invensas Corporation
    Inventors: Liang Wang, Rajesh Katkar, Javier A. Delacruz, Ilyas Mohammed, Belgacem Haba
  • Publication number: 20210149586
    Abstract: Some embodiments provide a three-dimensional (3D) circuit that has data lines of one or more memory circuits on a different IC die than the IC die(s) on which the memory blocks of the memory circuit(s) are defined. In some embodiments, the 3D circuit includes a first IC die with a first set of two or more memory blocks that have a first set of data lines. The 3D circuit also includes a second IC die that is stacked with the first IC dies and that includes a second set of two or more memory blocks with a second set of data lines. The 3D circuit further includes a third IC die that is stacked with the first and second IC dies and that includes a third set of data lines, which connect through several z-axis connections with the first and second sets of data lines to carry data to and from the first and second memory block sets when data is being written to and read from the first and second memory block sets.
    Type: Application
    Filed: November 13, 2020
    Publication date: May 20, 2021
    Inventors: Javier A. DeLaCruz, David E. Fisch
  • Publication number: 20210143125
    Abstract: A microelectronic assembly may include a semiconductor wafer having first and second surfaces extending in first and second directions, the semiconductor wafer having network nodes connected to one another via local adjacent connections each extending in only one of the first and second directions, and an interconnection structure comprising a low-loss dielectric material and having first and second opposite surfaces extending in third and fourth directions each oriented at an oblique angle relative to the first and second directions, the interconnection structure having local oblique connections each extending in only one of the third and fourth directions. The semiconductor wafer may be directly bonded to the interconnection structure such that each of the network nodes is connected with at least one of the other network nodes, without use of conductive bonding material, through at least one of the local adjacent connections and at least one of the local oblique connections.
    Type: Application
    Filed: November 7, 2019
    Publication date: May 13, 2021
    Inventors: Javier A. Delacruz, Richard E. Perego
  • Publication number: 20210134689
    Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.
    Type: Application
    Filed: January 11, 2021
    Publication date: May 6, 2021
    Inventors: Shaowu Huang, Javier A. DeLaCruz, Liang Wang, Rajesh Katkar, Belgacem Haba
  • Patent number: 10998265
    Abstract: A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.
    Type: Grant
    Filed: October 11, 2019
    Date of Patent: May 4, 2021
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier A. DeLaCruz
  • Patent number: 10991676
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Grant
    Filed: March 10, 2020
    Date of Patent: April 27, 2021
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 10991804
    Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: April 27, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, David Edward Fisch
  • Publication number: 20210118864
    Abstract: The present disclosure provides for a stacked memory combining RAM and one or more layers of NVM, such as NAND. For example, a first layer of RAM, such as DRAM, is coupled to multiple consecutive layers of NAND using direct bonding interconnect (DBI®). Serialization and overhead that exists in periphery of the NVM may be stripped to manage the data stored therein. The resulting connections between the RAM and the NVM are high bandwidth, high pincount interconnects. Interconnects between each of the one or more layers of NVM are also very dense.
    Type: Application
    Filed: October 14, 2020
    Publication date: April 22, 2021
    Inventors: Javier A. Delacruz, Pearl Po-Yee Cheng, David Edward Fisch
  • Patent number: 10978348
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: April 13, 2021
    Assignee: Xcelsis Corporation
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed
  • Publication number: 20210104436
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by stacking two or more integrated circuit (IC) dies to at least partially overlap and to share one or more interconnect layers that distribute power, clock and/or data-bus signals. The shared interconnect layers include interconnect segments that carry power, clock and/or data-bus signals. In some embodiments, the shared interconnect layers are higher level interconnect layers (e.g., the top interconnect layer of each IC die). In some embodiments, the stacked IC dies of the 3D circuit include first and second IC dies. The first die includes a first semiconductor substrate and a first set of interconnect layers defined above the first semiconductor substrate. Similarly, the second IC die includes a second semiconductor substrate and a second set of interconnect layers defined above the second semiconductor substrate.
    Type: Application
    Filed: November 19, 2020
    Publication date: April 8, 2021
    Inventors: Javier DeLaCruz, Steven L. Teig, Ilyas Mohammed, Eric M. Nequist