Patents by Inventor Javier A. Delacruz

Javier A. Delacruz has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10446487
    Abstract: A stacked and electrically interconnected structure is disclosed. The stacked structure can include a first element comprising a first contact pad and a second element comprising a second contact pad. The first contact pad and the second contact pad can be electrically and mechanically connected to one another by an interface structure. The interface structure can comprise a passive equalization circuit that includes a resistive electrical pathway between the first contact pad and the second contact pad and a capacitive electrical pathway between the first contact pad and the second contact pad. The resistive electrical pathway and the capacitive electrical pathway form an equivalent parallel resistor-capacitor (RC) equalization circuit.
    Type: Grant
    Filed: September 19, 2017
    Date of Patent: October 15, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier DeLaCruz
  • Publication number: 20190305093
    Abstract: A microelectronic unit may include an epitaxial silicon layer having a source and a drain, a buried oxide layer beneath the epitaxial silicon layer, an ohmic contact extending through the buried oxide layer, a dielectric layer beneath the buried oxide layer, and a conductive element extending through the dielectric layer. The source and the drain may be doped portions of the epitaxial silicon layer. The ohmic contact may be coupled to a lower surface of one of the source or the drain. The conductive element may be coupled to a lower surface of the ohmic contact. A portion of the conductive element may be exposed at the second dielectric surface of the dielectric layer. The second dielectric surface may be directly bonded to an external component to form a microelectronic assembly.
    Type: Application
    Filed: February 1, 2019
    Publication date: October 3, 2019
    Inventors: Javier A. Delacruz, David Edward Fisch
  • Patent number: 10403599
    Abstract: Embedded organic interposers for high bandwidth are provided. Example embedded organic interposers provide thick conductors with more dielectric space, and more routing layers of such conductors than conventional interposers, in order to provide high bandwidth transmission capacity over longer spans. The embedded organic interposers provide high bandwidth transmission paths between components such as HBM, HBM2, and HBM3 memory stacks, and other components. To provide the thick conductors and more routing layers for greater transmission capacity, extra space is achieved by embedding the organic interposers in the core of the package. Example embedded organic interposers lower a resistive-capacitive (RC) load of the routing layers to provide improved signal transmission of 1-2 GHz up to 20-60 GHz bandwidth for each 15 mm length, for example. The embedded organic interposers are not limited to use with memory modules.
    Type: Grant
    Filed: April 27, 2017
    Date of Patent: September 3, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba
  • Patent number: 10403577
    Abstract: Dielets on flexible and stretchable packaging for microelectronics are provided. Configurations of flexible, stretchable, and twistable microelectronic packages are achieved by rendering chip layouts, including processors and memories, in distributed collections of dielets implemented on flexible and/or stretchable media. High-density communication between the dielets is achieved with various direct-bonding or hybrid bonding techniques that achieve high conductor count and very fine pitch on flexible substrates. An example process uses high-density interconnects direct-bonded or hybrid bonded between standard interfaces of dielets to create a flexible microelectronics package. In another example, a process uses high-density interconnections direct-bonded between native interconnects of the dielets to create the flexible microelectronics packages, without the standard interfaces.
    Type: Grant
    Filed: May 3, 2018
    Date of Patent: September 3, 2019
    Assignee: Invensas Corporation
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Publication number: 20190265411
    Abstract: Integrated optical waveguides, direct-bonded waveguide interface joints, optical routing and interconnects are provided. An example optical interconnect joins first and second optical conduits. A first direct oxide bond at room temperature joins outer claddings of the two optical conduits and a second direct bond joins the inner light-transmitting cores of the two conduits at an annealing temperature. The two low-temperature bonds allow photonics to coexist in an integrated circuit or microelectronics package without conventional high-temperatures detrimental to microelectronics. Direct-bonded square, rectangular, polygonal, and noncircular optical interfaces provide better matching with rectangular waveguides and better performance. Direct oxide-bonding processes can be applied to create running waveguides, photonic wires, and optical routing in an integrated circuit package or in chip-to-chip optical communications without need for conventional optical couplers.
    Type: Application
    Filed: January 14, 2019
    Publication date: August 29, 2019
    Inventors: Shaowu HUANG, Javier A. DELACRUZ, Liang WANG, Guilian GAO
  • Publication number: 20190252375
    Abstract: A microelectronic circuit structure comprises a stack of bonded layers comprising a bottom layer and at least one upper layer. At least one of the upper layers comprises an oxide layer having a back surface and a front surface closer to the bottom layer than the back surface, and a plurality of FD-SOI transistors built on the front surface. At least a first back gate line and a second back gate line extend separate from each other above the back surface for independently providing a first back gate bias to a first group of transistors and a second back gate bias to a second different group of transistors.
    Type: Application
    Filed: February 9, 2018
    Publication date: August 15, 2019
    Inventors: Javier A. DELACRUZ, David Edward FISCH, Kenneth DUONG, Xu CHANG, Liang WANG
  • Publication number: 20190244899
    Abstract: A bonded device structure including a first substrate having a first set of conductive contact structures, preferably connected to a device or circuit, and having a first non-metallic region adjacent to the contact structures on the first substrate, a second substrate having a second set of conductive contact structures, preferably connected to a device or circuit, and having a second non-metallic region adjacent to the contact structures on the second substrate, and a contact-bonded interface between the first and second set of contact structures formed by contact bonding of the first non-metallic region to the second non-metallic region. The contact structures include elongated contact features, such as individual lines or lines connected in a grid, that are non-parallel on the two substrates, making contact at intersections. Alignment tolerances are thus improved while minimizing dishing and parasitic capacitance.
    Type: Application
    Filed: April 18, 2019
    Publication date: August 8, 2019
    Inventors: Paul M. Enquist, Gaius Gillman Fountain, JR., Javier A. DeLaCruz
  • Publication number: 20190221510
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Applicant: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Patent number: 10354945
    Abstract: Multi-surface edge pads for vertical mount packages and methods of making package stacks are provided. Example substrates for vertical surface mount to a motherboard have multi-surface edge pads. The vertical mount substrates may be those of a laminate-based FlipNAND. The multi-surface edge pads have cutouts or recesses that expose more surfaces and more surface area of the substrate for bonding with the motherboard. The cutouts in the edge pads allow more solder to be used between the attachment surface of the substrate and the motherboard. The placement and geometry of the resulting solder joint is stronger and has less internal stress than conventional solder joints for vertical mounting. In an example process, blind holes can be drilled into a thickness of a substrate, and the blind holes plated with metal. The substrate can be cut in half though the plated holes to provide two substrates with plated multi-surface edge pads including the cutouts for mounting to the motherboard.
    Type: Grant
    Filed: July 26, 2017
    Date of Patent: July 16, 2019
    Assignee: Invensas Corporation
    Inventors: Rajesh Katkar, Min Tao, Javier A. Delacruz, Hoki Kim, Akash Agrawal
  • Publication number: 20190214353
    Abstract: Vertical capacitors for microelectronics are provided. An example thin capacitor layer can provide one or numerous capacitors to a semiconductor chip or integrated circuit. In an implementation, a thin capacitor layer of 50-100 ?m thickness may have 5000 vertically disposed capacitor plates per linear centimeter, while occupying only a thin slice of the package. Electrodes for each capacitor plate are accessible at multiple surfaces. Electrode density for very fine pitch interconnects can be in the range of 2-200 ?m separation between electrodes. A redistribution layer (RDL) may be fabricated on one or both sides of the thin capacitor layer to provide fan-out ball grid arrays that occupy insignificant space. RDLs or through-vias can connect together sets of the interior vertical capacitor plates within a given thin capacitor layer to form various capacitors from the plates to meet the needs of particular chips, dies, integrated circuits, and packages.
    Type: Application
    Filed: December 12, 2018
    Publication date: July 11, 2019
    Applicant: Invensas Corporation
    Inventors: Belgacem Haba, Javier A. Delacruz
  • Publication number: 20190198407
    Abstract: An integrated device package is disclosed. The integrated device package can include an integrated device die, an element, a cavity, and an electrical interconnect. The element can have an antenna structure. The element can be attached to a surface of the integrated device. The cavity can be disposed between the integrated device die and the antenna structure. The electrical interconnect can connect the integrated device die and the antenna structure.
    Type: Application
    Filed: December 6, 2018
    Publication date: June 27, 2019
    Inventors: Shaowu Huang, Javier A. DeLaCruz, Liang Wang, Rajesh Katkar, Belgacem Haba
  • Patent number: 10325877
    Abstract: In a vertically integrated microelectronic package, a first microelectronic device is coupled to an upper surface of a circuit platform in a wire bond-only surface area thereof. Wire bond wires are coupled to and extends away from an upper surface of the first microelectronic device. A second microelectronic device in a face-down orientation is coupled to upper ends of the wire bond wires in a surface mount-only area. The second microelectronic device is located above and at least partially overlaps the first microelectronic device. A protective layer is disposed over the circuit platform and the first microelectronic device. An upper surface of the protective layer has the surface mount-only area. The upper surface of the protective layer has the second microelectronic device disposed thereon in the face-down orientation in the surface mount-only area for coupling to the upper ends of the first wire bond wires.
    Type: Grant
    Filed: April 23, 2018
    Date of Patent: June 18, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Abiola Awujoola, Ashok S. Prabhu, Christopher W. Lattin, Zhuowen Sun
  • Publication number: 20190181107
    Abstract: Representative implementations of techniques and devices are used to remedy or mitigate the effects of damaged interconnect pads of bonded substrates. A recess of predetermined size and shape is formed in the surface of a second substrate of the bonded substrates, at a location that is aligned with the damaged interconnect pad on the first substrate. The recess encloses the damage or surface variance of the pad, when the first and second substrates are bonded.
    Type: Application
    Filed: November 13, 2018
    Publication date: June 13, 2019
    Inventors: Javier A. DELACRUZ, Rajesh KATKAR, Shaowu HUANG, Gaius Gillman FOUNTAIN, JR., Liang WANG, Laura Wills MIRKARIMI
  • Patent number: 10295588
    Abstract: The invention pertains to in-wafer testing of integrated circuits. In particular, it pertains to apparatuses and methods for testing small integrated circuits that have pad sizes and pitches that are too small for using conventional wafer probing technology.
    Type: Grant
    Filed: December 22, 2016
    Date of Patent: May 21, 2019
    Assignee: Xcelsis Corporation
    Inventors: Javier A. Delacruz, William C. Plants
  • Patent number: 10299368
    Abstract: Apparatus, and corresponding method, relates generally to a microelectronic device. In such an apparatus, a first conductive layer is for providing a lower interior surface of a circuit structure. A plurality of wire bond wires are interconnected to the lower interior surface and spaced apart from one another for providing at least one side of the circuit structure. A second conductive layer is for providing an upper interior surface of the circuit structure spaced apart from the lower interior surface by and interconnected to the plurality of wire bond wires. The plurality of wire bond wires, the first conductive layer and the second conductive layer in combination define at least one opening in the at least one side for a signal port of the circuit structure. Such circuit structure may be a signal guide circuit structure, such as for a signal waveguide or signal cavity for example.
    Type: Grant
    Filed: December 21, 2016
    Date of Patent: May 21, 2019
    Assignee: Invensas Corporation
    Inventors: Shaowu Huang, Javier A. Delacruz
  • Patent number: 10290612
    Abstract: A three-dimensional stacking technique performed in a wafer-to-wafer fashion reducing the machine movement in production. The Wafers are processed with metallic traces and stacked before dicing into separate die stacks. The traces of each layer of the stacks are interconnected via electroless plating.
    Type: Grant
    Filed: May 30, 2018
    Date of Patent: May 14, 2019
    Assignee: Invensas Corporation
    Inventors: Belgacem Haba, Ilyas Mohammed, Javier A. Delacruz
  • Patent number: 10283445
    Abstract: A microelectronic assembly including first and second laminated microelectronic elements is provided. A patterned bonding layer is disposed on a face of each of the first and second laminated microelectronic elements. The patterned bonding layers are mechanically and electrically bonded to form the microelectronic assembly.
    Type: Grant
    Filed: October 26, 2016
    Date of Patent: May 7, 2019
    Assignee: Invensas Corporation
    Inventors: Javier A. Delacruz, Belgacem Haba, Wael Zohni, Liang Wang, Akash Agrawal
  • Patent number: 10276909
    Abstract: A structure can include a first element and a carrier bonded to the first element along an interface. A waveguide can be defined at least in part along the interface between the first element and the carrier. The waveguide can comprise an effectively closed metallic channel and a dielectric material within the effectively closed metallic channel, as viewed from a side cross-section of the structure. Various millimeter-wave or sub-terahertz components or circuit structures can also be created based on the waveguide structures disclosed herein.
    Type: Grant
    Filed: December 30, 2016
    Date of Patent: April 30, 2019
    Assignee: Invensas Bonding Technologies, Inc.
    Inventors: Shaowu Huang, Javier A. DeLaCruz, Belgacem Haba
  • Publication number: 20190123024
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers.
    Type: Application
    Filed: October 14, 2018
    Publication date: April 25, 2019
    Inventors: Steven L. Teig, Ilyas Mohammed, Kenneth Duong, Javier DeLaCruz
  • Publication number: 20190123023
    Abstract: Some embodiments of the invention provide a three-dimensional (3D) circuit that is formed by vertically stacking two or more integrated circuit (IC) dies to at least partially overlap. In this arrangement, several circuit blocks defined on each die (1) overlap with other circuit blocks defined on one or more other dies, and (2) electrically connect to these other circuit blocks through connections that cross one or more bonding layers that bond one or more pairs of dies. In some embodiments, the overlapping, connected circuit block pairs include pairs of computation blocks and pairs of computation and memory blocks. The connections that cross bonding layers to electrically connect circuit blocks on different dies are referred to below as z-axis wiring or connections. This is because these connections traverse completely or mostly in the z-axis of the 3D circuit, with the x-y axes of the 3D circuit defining the planar surface of the IC die substrate or interconnect layers.
    Type: Application
    Filed: October 14, 2018
    Publication date: April 25, 2019
    Inventors: Steven L. Teig, Ilyas Mohammed, Kenneth Duong, Javier DeLaCruz