Patents by Inventor Jawad B. Khan

Jawad B. Khan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210326254
    Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
    Type: Application
    Filed: April 1, 2021
    Publication date: October 21, 2021
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Publication number: 20210318805
    Abstract: Binary sparse encoding of data can be used to reduce an amount of data read from the stochastic associative memory while processing a query. Read performance of the stochastic associated memory is optimized to enhance the query throughput by modifying access patterns to reduce the time to read the stochastic associated memory. Read performance of the stochastic associative memory can be further improved through the use of cluster aware sharding and replication for parallelized similarity search. Clusters are partitioned across multiple Dual In-line Memory Modules (DIMMs), each DIMM including stochastic associative memory, to achieve maximum latency advantage.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 14, 2021
    Inventors: Sourabh DONGAONKAR, Jawad B. KHAN, Chetan CHAUHAN, Dipanjan SENGUPTA, Mariano TEPPER, Theodore WILLKE
  • Publication number: 20210311659
    Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.
    Type: Application
    Filed: June 17, 2021
    Publication date: October 7, 2021
    Inventors: Peng LI, Jawad B. KHAN, Sanjeev N. TRIKA
  • Publication number: 20210294799
    Abstract: Methods and apparatus for sparse column-aware encodings for numeric data types, including integer data and floating-point data (float, double, etc.). The encoding schemes are tailored to take advantage of column addressable memories such as stochastic associative memories (SAM) to enable Stochastic Associative Search (SAS), which is a highly efficient and fast way of searching through a very large database of records (order of Billions) and finding similar records to a given query record (search key). Techniques are also disclosed for performing range searches for both integer and floating-point data types. The integer or float data is converted to Hexadecimal form and encoded using an m-of-n constant weight encoding. Only the columns with set bits in search keys need to be read, which significantly reduces the number of reads required for searches.
    Type: Application
    Filed: June 8, 2021
    Publication date: September 23, 2021
    Inventors: Wei WU, Sourabh DONGAONKAR, Jawad B. KHAN
  • Patent number: 11126374
    Abstract: Technologies for stochastic associative search operations in memory (e.g., a three-dimensional cross-point memory) include a compute device. The compute device has a memory including a matrix that stores individually addressable bit data and is formed by rows and columns. The compute device receives a request to retrieve a subset of the bit data stored in the matrix. The request includes a search key indicative of the subset of bit data, and the search key is formed on a same axis as the rows. The compute device identifies one or more candidate data sets in the matrix based on a search for matching bit data of the search key with bit data in one or more of the columns. The compute device outputs the identified candidate data sets.
    Type: Grant
    Filed: March 28, 2019
    Date of Patent: September 21, 2021
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Richard Coulson
  • Publication number: 20210286551
    Abstract: Examples described herein relate to an apparatus comprising: circuitry to receive a request to store data as a part of a matrix in a memory device; circuitry to allocate address mappings to the data to reduce a number of sequential accesses to a same partition of a portion of the memory device; circuitry to store the address mappings for access with a read operation; and circuitry to cause storage of the data into the memory device according to the address mappings. In some examples, the matrix comprises one or more columns and/or one or more rows. In some examples, the memory device comprises one or more of: a three-dimensional (3D) cross point memory device, volatile memory device, or non-volatile memory device.
    Type: Application
    Filed: June 2, 2021
    Publication date: September 16, 2021
    Inventors: Sourabh DONGAONKAR, Jawad B. KHAN
  • Publication number: 20210263895
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Application
    Filed: May 13, 2021
    Publication date: August 26, 2021
    Applicant: Intel Corporation
    Inventors: Sanjeev N. TRIKA, Jawad B. KHAN, Piotr WYSOCKI
  • Patent number: 11102902
    Abstract: Data storage system connectors are described for a parallel array of dense memory cards that allow high airflow. In one example, a connector has a horizontal plane board having a plurality of memory connectors aligned in a row and a plurality of external interfaces, a plurality of memory cards, each having an edge connector at one end of the memory card to connect to a respective memory connector of the board, each memory card extending horizontally parallel to each other memory card and extending vertically and orthogonally from the board, and a plurality of interface connectors each to connect an edge connector to a respective board connector, the interface connectors extending horizontally from the one end of the memory cards and vertically to the respective plane board connector.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: August 24, 2021
    Assignee: Intel Corporation
    Inventors: Michael D. Nelson, Jawad B. Khan, Randall K. Webb
  • Patent number: 11080226
    Abstract: Technologies for providing a scalable architecture to efficiently perform compute operations in memory include a memory having media access circuitry coupled to a memory media. The media access circuitry is to access data from the memory media to perform a requested operation, perform, with each of multiple compute logic units included in the media access circuitry, the requested operation concurrently on the accessed data, and write, to the memory media, resultant data produced from execution of the requested operation.
    Type: Grant
    Filed: January 8, 2020
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Shigeki Tomishima, Srikanth Srinivasan, Chetan Chauhan, Rajesh Sundaram, Jawad B. Khan
  • Patent number: 11079958
    Abstract: Provided are an apparatus, system and method for offloading data transfer operations between source and destination storage devices to a hardware accelerator. The hardware accelerator includes a memory space and control logic to receive, from a host processor, a command descriptor indicating at least one source storage device having transfer data to transfer to at least one destination storage device and a computational task to perform on the transfer data. The control logic sends read commands to the at least one source storage device to read the transfer data to at least one read buffer in the memory space and performs the computational task on the transfer data to produce modified transfer data. The control logic writes the modified transfer data to at least one write buffer in the memory space to cause the modified transfer data to be written to the at least one destination storage device.
    Type: Grant
    Filed: April 12, 2019
    Date of Patent: August 3, 2021
    Assignee: Intel Corporation
    Inventors: Divya Narayanan, Jawad B. Khan, Michael D. Nelson, Akshay G. Pethe
  • Patent number: 11074008
    Abstract: Technologies for performing a hyper-dimensional operation in a memory of the compute device include a memory and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to a receipt of the query, a key hyper-dimensional vector associated with the query, perform a hyper-dimensional operation to determine a reference hyper-dimensional vector associated with a value to the key. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array of a hyper-dimensional vector table in the memory, identify a closest matching row in the stochastic associative array relative to the reference hyper-dimensional vector, wherein the closest matching row indicates a closest matching value hyper-dimensional vector, and output a value associated with the closest matching value hyper-dimensional vector.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: July 27, 2021
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Richard Coulson
  • Publication number: 20210224267
    Abstract: Technologies for tuning performance and/or accuracy of similarity search using stochastic associative memories (SAM). Under a first subsampling approach, columns associated with set bits in a search key comprising a binary bit vector are subsampled. Matching set bits for the subsampled columns are aggregated on a row-wise basis to generate similarity scores, which are then ranked. A similar scheme is applied for all the columns with set bits in the search key and the results for top ranked rows are compared to evaluate a tradeoff between throughput boost versus lost accuracy. A second approach called continuous column read, and iterative approach is employed that continuously scores the rows as each new column read is complete. The similarity scores for an N-1 and Nth-1 iteration are ranked, a rank correlation is calculated, and a determination is made to whether the rank correlation meets or exceeds a threshold.
    Type: Application
    Filed: April 9, 2021
    Publication date: July 22, 2021
    Inventors: Sourabh DONGAONKAR, Jawad B. KHAN, Chetan CHAUHAN, Dipanjan SENGUPTA, Mariano TEPPER, Theodore WILLKE, Richard L. COULSON
  • Patent number: 11042323
    Abstract: A host-managed storage device includes an offload capability that enables the host to offload all or a portion of a defrag operation to the storage device. Rather than issuing read, write or copy operations and commands to relocate data to the host's DRAM, the host assembles a defrag operation command descriptor for the storage device controller. The command descriptor includes a defrag bitmap that can be directly accessed by the storage device controller to conduct the defrag operation entirely on the storage device at band granularity, without consuming host CPU cycles or host memory. The reduction in host operations/commands achieved by offloading defragmentation to the storage device is on the order of at least a thousand-fold reduction.
    Type: Grant
    Filed: June 29, 2019
    Date of Patent: June 22, 2021
    Assignee: Intel Corporation
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 11023320
    Abstract: Technologies for providing multiple levels of error correction include a memory that includes media access circuitry coupled to a memory media. The media access circuitry is to read data from the memory media. Additionally, the media access circuitry is to perform, with an error correction logic unit located in the media access circuitry, error correction on the read data to produce error-corrected data.
    Type: Grant
    Filed: April 4, 2019
    Date of Patent: June 1, 2021
    Assignee: Intel Corporation
    Inventors: Wei Wu, Rajesh Sundaram, Chetan Chauhan, Jawad B. Khan, Shigeki Tomishima, Srikanth Srinivasan
  • Patent number: 11010350
    Abstract: Examples may include a storage appliance having a mass storage device and a compute engine communicating peer-to-peer with each other, with the compute engine including a programmable logic component to execute a function to read data from the at least one storage device, process the data; and write data to the at least one storage device.
    Type: Grant
    Filed: January 27, 2020
    Date of Patent: May 18, 2021
    Assignee: INTEL CORPORATION
    Inventors: Sanjeev N. Trika, Jawad B. Khan, Piotr Wysocki
  • Patent number: 10970207
    Abstract: An embodiment of a semiconductor package apparatus may include technology to provide a first interface between a first storage device and a host device, and provide a second interface directly between the first storage device and a second storage device. Other embodiments are disclosed and claimed.
    Type: Grant
    Filed: September 27, 2019
    Date of Patent: April 6, 2021
    Assignee: Intel Corporation
    Inventors: Peng Li, Jawad B. Khan, Sanjeev N. Trika
  • Patent number: 10949214
    Abstract: Technologies for performing hyper-dimensional operations in memory includes a device with a memory media and a memory controller. The memory controller is configured to receive a query from a requestor and determine, in response to receiving the query, a reference hyper-dimensional vector associated with the query. The memory controller is further configured to perform a nearest neighbor search by searching columns of a stochastic associative array in the memory media to determine a number of matching bit values for each row relative to the reference hyper-dimensional vector, wherein each bit in a column of the stochastic associative array represents a bit value of a corresponding row, identify a closest matching row that has a highest number of matching bit values, and output data of the closest matching row.
    Type: Grant
    Filed: March 29, 2019
    Date of Patent: March 16, 2021
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Richard Coulson
  • Patent number: 10942847
    Abstract: Technologies for efficiently performing scatter-gather operations include a device with circuitry configured to associate, with a template identifier, a set of non-contiguous memory locations of a memory having a cross point architecture. The circuitry is additionally configured to access, in response to a request that identifies the non-contiguous memory locations by the template identifier, the memory locations.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: March 9, 2021
    Assignee: Intel Corporation
    Inventors: Jawad B. Khan, Richard Coulson
  • Patent number: 10915267
    Abstract: Examples include techniques for implementing a write transaction to two or more memory devices in a storage device. In some examples, the write transaction includes an atomic write transaction from an application or operating system executing on a computing platform to a storage device coupled with the computing platform. For these examples, the storage device includes a storage controller to receive an atomic multimedia write transaction request to write first data and second data; cause the first data to be stored in a first memory device, and cause the second data to be stored in a second memory device, simultaneously and atomically.
    Type: Grant
    Filed: December 6, 2017
    Date of Patent: February 9, 2021
    Assignee: INTEL CORPORATION
    Inventors: Sanjeev N. Trika, Peng Li, Jawad B. Khan, Myron Loewen
  • Publication number: 20210007235
    Abstract: Data storage system connectors are described for a parallel array of dense memory cards that allow high airflow. In one example, a connector has a horizontal plane board having a plurality of memory connectors aligned in a row and a plurality of external interfaces, a plurality of memory cards, each having an edge connector at one end of the memory card to connect to a respective memory connector of the board, each memory card extending horizontally parallel to each other memory card and extending vertically and orthogonally from the board, and a plurality of interface connectors each to connect an edge connector to a respective board connector, the interface connectors extending horizontally from the one end of the memory cards and vertically to the respective plane board connector.
    Type: Application
    Filed: July 17, 2020
    Publication date: January 7, 2021
    Inventors: Michael D. NELSON, Jawad B. KHAN, Randall K. WEBB