Abstract: A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transferer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the values for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.

Abstract: A computer that provides data to a video display using a bitmap display memory organization and bitplane addressing. Separate control is provided for two bitplane backgrounds and for eight reusable and easily movable sprites. Additional logic allows for dynamically-controllable interobject priority and collision detection among data in each of the bitplane backgrounds and sprites. A coprocessor provides for video beam-synchronized changes to data in registers, freeing the main processor for general purpose computing tasks. A block image transfer is provided to rapidly copy data in large blocks from one memory location to another. In hold-and-modify mode, color output circuitry holds the value for a previously displayed pixel while bitplane data modifies those values, allowing for simultaneous display of a greatly increased number of colors.

Abstract: A peripheral control circuit for a computer system. Independent control and interface circuits are provided for left and right audio channels, for a communications port, for storage media, and for joysticks or paddles. Control logic is provided for direct memory access to system memory and for interrupts to the processor by each of the peripherals. Sound data corresponding to a sound waveform during a particular time period is fetched using DMA or interrupts. Registers store data for selecting the output rate of the sound data, the length of the sound waveform, and the volume of the sound waveform. Four audio channels and two separate audio ports are provide.

Abstract: A video game home computer is implemented in NMOS (n type metal oxide semiconductor) technology with plural microprocessors. Centralized bus architecture and direct memory access (DMA) techniques are employed. A video display generator provides color signal outputs to drive a commercial television receiver display. This display generator receives inputs from both microprocessors and obtains data directly from memory. A bit map of display information is kept in memory, wherein bits of information in memory image the precise screen display for each instance in time. A bit map manipulator circuit performs, under microprocessor direction, logic function manipulation of the bit map data. Access between system components is accomplished via the bus architecture on a priority queue basis. Chip count and chip area is minimized.

Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and a display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.

Abstract: A microprocessor based data processing system including a microprocessor, a memory unit, and display unit is provided with a programmable graphics generator that transfers graphics information from the memory unit to the display unit in response to and control of a set of display instructions also stored in the memory unit. The graphics generator includes a first addressing unit for sequentially accessing the display instructions from the memory unit; a control unit for receiving, storing and decoding such instruction and for issuing supervisory and control signals in response to the binary state of each instruction; a second addressing unit for accessing graphics information from the memory unit in response to the supervisory signals from the control unit; and a third addressing unit for accessing movable object graphics stored in the memory unit.