Abstract: Examples are provided for a method and apparatus for calibration of an analog-to-digital converter (ADC) including multiple sub-ADCs. The method includes applying a calibration signal to an input node of each sub-ADC. For each sub-ADC, a corresponding error signal is generated based on output signals of the sub-ADC and a reference sub-ADC. Each sub-ADC is calibrated based on the corresponding error signal. The reference sub-ADC is selected by: applying a non-zero input voltage signal to the input node of each sub-ADC, measuring a corresponding output signal of each sub-ADC in response to the non-zero input voltage signal, generating a deviation error based on a subtraction of a stored value from the measured output signal of each sub-ADC, and designating as the reference sub-ADC a sub-ADC from the multiple sub-ADCs based on the deviation error.

Abstract: Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).

Abstract: Methods, systems and devices described herein improve vertical resolution at sides of a four cornered image produced by a scanning projector display device. In accordance with an embodiment, a first plurality of frames (e.g., odd frames) of the image are scanned back and forth from side to side starting at a first line level, in one of the corners. Additionally, a second plurality of frames (e.g., even frames) of the image are scanned back and forth from side to side, starting at a vertical offset level from the first line level, in the same one of the corners. The scanning of the first plurality of frames (e.g., the odd frames) is interleaved with the scanning of the second plurality of frames (e.g., the even frames).

Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator and being operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal and includes a synchronous output switch having a phase node therebetween controlled by the gate driver, and also including regulator input current measurement circuitry. The regulator input current measurement circuitry includes a circuit that provides a signal representative of at least one phase node timing parameter. A sensing circuit is operable to sense inductor or output current provided by the regulator. A calculation circuit is coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current from the phase node timing parameters and the inductor or output current.

Abstract: An embodiment of a hysteretic power-supply controller includes a signal generator, frequency adjuster, and signal combiner. The signal generator is operable to generate a switching signal having a first level in response to a control signal being greater than a first reference value and having a second level in response to the control signal being less than a second reference value, the switching signal having an actual frequency and being operable to drive a switching stage that generates a regulated output signal. The frequency adjuster is operable to generate a frequency-adjust signal that is related to a difference between the actual frequency and a desired frequency. And the signal combiner is operable to generate the control signal from the frequency-adjust signal and the regulated output signal. Such a hysteretic power-supply controller may allow one to set the switching frequency to a desired value independently of the parameters of the power supply.

Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.

Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.

Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.

Abstract: A synchronous regulator includes a controller coupled to receive a reference signal and a feedback signal from the regulator operable to provide a pulse width modulation (PWM) signal at its output. The regulator includes at least one gate driver coupled to receive the PWM signal, and a synchronous output switch having a phase node there between controlled by the gate driver, and regulator input current measurement circuitry. The regulator input current measurement circuitry comprises a circuit operable for providing a signal representative of at least one phase node timing parameter, a sensing circuit operable for sensing inductor or output current provided by the regulator, and a calculation circuit coupled to receive the signal representative of the phase node timing parameters and the inductor or output current and is operable to determine the input current.

Abstract: A circuit comprises a digital phase locked loop for generating a synchronization signal and a voltage regulator for providing regulated output voltage responsive to the synchronization signal from the digital phase locked loop.