Patents by Inventor Jayavel Pachamuthu

Jayavel Pachamuthu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220115343
    Abstract: A semiconductor device including an integrated module formed of a first semiconductor die coupled to a second semiconductor die. Each of the first and second semiconductor dies includes a number of bond pads, which are bonded to each other to form the integrated module. Each bond pad may be divided into a number of discrete pad legs. While the overall footprint of each bond pad on the first and second semiconductor dies may be the same, the bond pads on one of the dies may have a larger number of pad legs.
    Type: Application
    Filed: February 12, 2021
    Publication date: April 14, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Publication number: 20220108926
    Abstract: A system and method for die crack detection in a CMOS bonded array includes a capacitor that is formed in an edge seal, where one of the capacitor plates is in the edge seal portion of a first wafer, and the other capacitor plate is in the edge seal portion of a second wafer. A crack in the die can be detected by applying an alternating current waveform to a testing contact on the integrated circuit and monitoring for a shift in the alternating current waveform, as a crack would cause modulation in the capacitance.
    Type: Application
    Filed: February 22, 2021
    Publication date: April 7, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Jayavel Pachamuthu, Kirubakaran Periyannan, Daniel Linnen
  • Publication number: 20220093476
    Abstract: A system and method for warpage detection in a CMOS bonded array includes a conductor positioned between bonded contact pads of first and second wafers. The conductor is connected to a continuity check circuit. If the continuity check circuit detects an interruption in conductivity of the conductor, such interruption is indicative of warpage in the first and/or second wafers. In one implementation, the conductor is a serpentine-shaped structure.
    Type: Application
    Filed: February 22, 2021
    Publication date: March 24, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Publication number: 20220084979
    Abstract: A method including stacking a number of silicon dice such that one or more edges of the dice are in vertical alignment, where the one or more edges include a number of connection pads. The method also includes positioning a connecting wire on a substantially perpendicular axis to the one or more edges. The connecting wire includes a number of solder blocks formed thereon. The solder blocks are spaced at intervals associated with a distance between a first set of aligned connection pads on the dice. The connecting wire is positioned such that the solder blocks are in contact with the first set of aligned connection pads. The method also includes applying heat to cause the solder blocks to reflow and physically and electrically couple the connecting wire to the connection pads.
    Type: Application
    Filed: February 9, 2021
    Publication date: March 17, 2022
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Patent number: 11222865
    Abstract: The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.
    Type: Grant
    Filed: May 12, 2020
    Date of Patent: January 11, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Publication number: 20210389901
    Abstract: A memory controller includes, in one embodiment, a memory interface and a controller circuit. The memory interface is configured to interface with a memory interface configured to interface with a memory having a plurality of memory blocks. Each memory block has a plurality of strings. The controller circuit is configured to perform a string defect leakage check on one of the memory blocks during a first programming operation of the one memory block, determine whether the one memory block has one or more string to string shorts based on the string defect leakage check, and resolve the string to string shorts in response to determining that the one of the memory blocks has the string to string shorts.
    Type: Application
    Filed: June 10, 2020
    Publication date: December 16, 2021
    Inventors: Jayavel Pachamuthu, Rajan Paudel, Deepak Bharadwaj
  • Patent number: 11195820
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: December 7, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran Cr, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Publication number: 20210358886
    Abstract: The present technology relates to a semiconductor device including semiconductor dies formed with vertical die bond pads on an edge of the dies. During wafer fabrication, vertical bond pad blocks are formed in scribe lines of the wafer and electrically coupled to the die bond pads of the semiconductor dies. The vertical bond pad blocks are cut through during wafer dicing, thereby leaving large, vertically oriented pads exposed on a vertical edge of each semiconductor die.
    Type: Application
    Filed: May 12, 2020
    Publication date: November 18, 2021
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Kirubakaran Periyannan, Daniel Linnen, Jayavel Pachamuthu
  • Patent number: 11164883
    Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, and memory stack structures extending through the alternating stack. Each of the memory stack structures comprises a memory film and a vertical semiconductor channel contacting an inner sidewall of the memory film. The electrically conductive layers include aluminum and silicon and provide low resistance electrically conductive paths as word lines of the three-dimensional memory device. The aluminum-based electrically conductive layers can provide low resistivity, low mechanical stress, and thermal stability for use as high performance word lines.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: November 2, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Peter Rabkin, Masaaki Higashitani, Jayavel Pachamuthu
  • Patent number: 11139276
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Grant
    Filed: March 3, 2020
    Date of Patent: October 5, 2021
    Assignee: SanDisk Technologies LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran Cr, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Publication number: 20210280559
    Abstract: A fractured semiconductor die is disclosed, together with a semiconductor device including the fractured semiconductor die. During fabrication of the semiconductor dies in a wafer, the wafer may be scored in a series of parallel scribe lines through portions of each row of semiconductor dies. The scribe lines then propagate through the full thickness of the wafer to fracture off a portion of each of the semiconductor dies. It may happen that electrical traces such as bit lines in the memory cell arrays short together during the die fracture process. These electrical shorts may be cleared by running a current through each of the electrical traces.
    Type: Application
    Filed: March 3, 2020
    Publication date: September 9, 2021
    Applicant: SANDISK TECHNOLOGIES LLC
    Inventors: Daniel Linnen, Kirubakaran Periyannan, Jayavel Pachamuthu, Narendhiran CR, Jay Dholakia, Everett Lyons, IV, Hoang Huynh, Dat Dinh
  • Patent number: 11107540
    Abstract: Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier including a first plurality of memory cells and the upper tier including a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.
    Type: Grant
    Filed: February 14, 2020
    Date of Patent: August 31, 2021
    Assignee: Sandisk Technologies LLC
    Inventors: Jayavel Pachamuthu, Dengtao Zhao
  • Patent number: 11101284
    Abstract: A method of forming a semiconductor structure includes providing a dopant species selected from carbon, boron, nitrogen or oxygen into an upper portion of a semiconductor region to form a doped etch stop semiconductor material portion over a remaining semiconductor material portion, forming an overlying material portion over the etch stop semiconductor material portion, etching through the overlying material portion by an etch process that removes the overlying material portion selective to a material of the etch stop semiconductor material portion, and depositing at least one fill material over the etch stop semiconductor material portion.
    Type: Grant
    Filed: December 18, 2018
    Date of Patent: August 24, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Hiroyuki Kinoshita, Masaaki Higashitani, Makoto Dei, Junji Oh
  • Publication number: 20210257035
    Abstract: Techniques for reducing program disturb of memory cells which are formed in a NAND string extending in a lower tier and an upper tier of a stack, the lower tier comprising a first plurality of memory cells and the upper tier comprising a second plurality of memory cells, wherein each memory cell of the first and second pluralities of memory cells is connected to a respective word line. The NAND string includes a joint region formed of a dielectric material and disposed between the lower tier and the upper tier of the stack; a first non-data memory cell adjacent to and below the joint region; a second non-data memory cell adjacent to and above the joint region; and a conductive gate connected to the first non-data memory cell and the second non-data memory cell.
    Type: Application
    Filed: February 14, 2020
    Publication date: August 19, 2021
    Inventors: Jayavel Pachamuthu, Dengtao Zhao
  • Patent number: 11037631
    Abstract: Strings of non-volatile memory cells include one or more joint regions adjacent to dummy non-volatile memory cells. During erase operations, different voltage levels are used for different dummy word lines coupled to respective dummy non-volatile memory cells. For example, a selection circuit may set a voltage level of a particular dummy word line to a voltage level greater than a different dummy word line. In another example, the selection circuit may determine a voltage level for a given dummy word line based on a distance between a non-volatile memory cell coupled to the given dummy word line and a selection device included in a string of non-volatile memory cells. Electron holes generated using the dummy word lines during erase operations may neutralize undesired trapped charges in a non-volatile memory string, thereby reducing disparity in erase times for different strings in the non-volatile memory circuit.
    Type: Grant
    Filed: January 18, 2019
    Date of Patent: June 15, 2021
    Assignee: Sandisk Technologies LLC
    Inventors: Jayavel Pachamuthu, Amul Dhirajbhai Desai, Ankitkumar Babariya
  • Patent number: 11024645
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film including a silicon nitride layer and a tunneling dielectric layer is formed in the memory opening, and an opening is formed through the memory film. A chemical oxide layer is formed on a physically exposed surface of an underlying semiconductor material portion. A silicon nitride ring can be formed by selectively growing a silicon nitride material from an annular silicon nitride layer portion of the silicon nitride layer while suppressing deposition of the silicon nitride material on the tunneling dielectric layer and on the chemical oxide layer. A vertical semiconductor channel can be formed by depositing a continuous semiconductor material layer on the underlying semiconductor material portion and the tunneling dielectric layer and on the silicon nitride ring.
    Type: Grant
    Filed: September 26, 2019
    Date of Patent: June 1, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Takumi Moriyama, Yasushi Dowaki, Yuki Kasai, Satoshi Shimizu, Jayavel Pachamuthu
  • Patent number: 10991718
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion. A connection strap is formed by performing a selective semiconductor deposition process that grows a strap semiconductor material from a physically exposed surface of an underlying semiconductor material portion through the opening. A vertical semiconductor channel is formed on an inner sidewall of the memory film by non-selectively depositing a semiconductor channel material. The connection strap provides an electrical connection between the underlying semiconductor material portion and the vertical semiconductor channel through the opening in the memory film. The sacrificial material layers are then replaced with electrically conductive layers.
    Type: Grant
    Filed: July 30, 2019
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Jayavel Pachamuthu, Hiroyuki Kinoshita, Marika Gunji-Yoneoka, Tadashi Nakamura, Tomohiro Oginoe
  • Patent number: 10991705
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Jayavel Pachamuthu
  • Patent number: 10991706
    Abstract: An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. A memory opening is formed through the alternating stack. An amorphous semiconductor material portion is formed at a bottom region of the memory opening. A memory film is formed in the memory opening. The memory film includes an opening at a bottom portion thereof, and a surface of the amorphous semiconductor material portion is physically exposed at a bottom of the opening in the memory film. An amorphous semiconductor channel material layer is formed on the exposed surface of the amorphous semiconductor material portion and over the memory film. A vertical semiconductor channel is formed by annealing the amorphous semiconductor material portion and the amorphous semiconductor channel material layer. The vertical semiconductor channel and contacts an entire top surface of an underlying semiconductor material portion.
    Type: Grant
    Filed: August 30, 2019
    Date of Patent: April 27, 2021
    Assignee: SANDISK TECHNOLOGIES LLC
    Inventors: Masatoshi Nishikawa, Jayavel Pachamuthu
  • Patent number: 10943662
    Abstract: An apparatus includes non-volatile memory and a control circuit configured to program the non-volatile memory. The control circuit is configured to change a programming order. In one aspect, the control circuit changes the order in which word lines are programmed from one point in time to another. In one aspect, the control circuit uses one order for programming one set of word lines and a different order for a different set of word lines. The sets of word lines could be in different sub-blocks, memory blocks, or memory dies. Such programming order differences can improve performance of error recovery.
    Type: Grant
    Filed: December 10, 2019
    Date of Patent: March 9, 2021
    Assignee: Western Digital Technologies, Inc.
    Inventors: Daniel Linnen, Jayavel Pachamuthu, Kirubakaran Periyannan