Abstract: An ESD protection circuit is provided. An embodiment provides an ESD protection circuit of a crystal oscillator for bearing an output swing level in an ESD IO for improving a reference clock isolation by adding a stacked diode to the ESD protection circuit and for improving a protection function by applying a secondary diode structure.

Abstract: An ESD protection circuit is provided. An embodiment provides an ESD protection circuit of a crystal oscillator for bearing an output swing level in an ESD IO for improving a reference clock isolation by adding a stacked diode to the ESD protection circuit and for improving a protection function by applying a secondary diode structure.

Abstract: Disclosed herein is a switching regulator with a soft start circuit for suppressing an in-rush current. The switching regulator includes a peak detector configured to receive a clock signal and detect a peak voltage of the clock signal, a comparator configured to generate a soft start signal for controlling a soft start of the switching regulator based on a result of comparing a level of the peak voltage of the clock signal to a preset reference voltage level, a counter configured to switch a state of the soft start signal at a time point when a preset soft start time arrives, and a ramp voltage generation unit configured to generate a ramp voltage by adjusting a resistance of a variable resistor based on the soft start signal.

Abstract: Disclosed are an apparatus for lock detection suitable for a fractional-N frequency synthesizer and a method thereof. The lock detector for use in the fractional-N frequency synthesizer includes a delay unit delaying an N-divider output frequency clock based on an output value of a fraction ratio modulator, a lock detection unit outputting a lock detection signal by comparing a reference frequency clock with the N-divider output frequency clock delayed by the delay unit, a counter counting the number of lock detection signals received from the lock detection unit, and a controller issuing a command to output a lock identification signal based on the number of lock detection signals counted by the counter.

Abstract: Disclosed are an apparatus for lock detection suitable for a fractional-N frequency synthesizer and a method thereof. The lock detector for use in the fractional-N frequency synthesizer includes a delay unit delaying an N-divider output frequency clock based on an output value of a fraction ratio modulator, a lock detection unit outputting a lock detection signal by comparing a reference frequency clock with the N-divider output frequency clock delayed by the delay unit, a counter counting the number of lock detection signals received from the lock detection unit, and a controller issuing a command to output a lock identification signal based on the number of lock detection signals counted by the counter.

Abstract: A low noise reference voltage circuit without using an amplifier inside is capable of transforming a current IPTAT in positive proportion to absolute temperature into a voltage VPTAT in positive proportion to absolute temperature, and outputting it to a ring oscillator. The low noise reference voltage circuit improves a degradation of noise performance compared with a conventional band-gap reference voltage circuit and is in characteristic of low noise and higher PSRR.

Abstract: A low noise reference voltage circuit without using an amplifier inside is capable of transforming a current IPTAT in positive proportion to absolute temperature into a voltage VPTAT in positive proportion to absolute temperature, and outputting it to a ring oscillator. The low noise reference voltage circuit improves a degradation of noise performance compared with a conventional band-gap reference voltage circuit and is in characteristic of low noise and higher PSRR.