Patents by Inventor Je-Young Park

Je-Young Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8254204
    Abstract: A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased or decreased at least one burst bit into an X burst bit and a Y burst bit, and a selector for receiving an X address, a Y address, the X burst bit, and the Y burst bit, and generating an X burst address based on the X address and the X burst bit and a Y burst address based on the Y address and the Y burst bit.
    Type: Grant
    Filed: July 6, 2010
    Date of Patent: August 28, 2012
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-young Park, Jae-young Choi, Hyoung-soon Km
  • Publication number: 20110158014
    Abstract: A burst address generator includes a burst bit counter for receiving at least one burst bit, and increasing or decreasing the at least one burst bit, a burst bit splitter for receiving the increased or decreased at least one burst bit from the burst bit counter, and dividing the increased or decreased at least one burst bit into an X burst bit and a Y burst bit, and a selector for receiving an X address, a Y address, the X burst bit, and the Y burst bit, and generating an X burst address based on the X address and the X burst bit and a Y burst address based on the Y address and the Y burst bit.
    Type: Application
    Filed: July 6, 2010
    Publication date: June 30, 2011
    Inventors: Je-young Park, Jae-young Choi, Hyoung-soon Km
  • Patent number: 7886206
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Grant
    Filed: March 31, 2009
    Date of Patent: February 8, 2011
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Young Park, Ki-Sang Kang
  • Publication number: 20090199059
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Application
    Filed: March 31, 2009
    Publication date: August 6, 2009
    Inventors: Je-Young Park, Ki-Sang Kang
  • Patent number: 7533310
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Grant
    Filed: December 19, 2006
    Date of Patent: May 12, 2009
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Je-Young Park, Ki-Sang Kang
  • Publication number: 20070162794
    Abstract: A semiconductor memory test device and method thereof are provided. The example semiconductor memory test device may include a fail memory configured to store at least one test result of a memory under test, a mode selecting unit configured to output a selection signal for selecting a memory address protocol of the fail memory based upon which one of a plurality of test modes is active in the memory under test and an address arranging unit configured to arrange address signals to conform with the selected memory address protocol in response to the selection signal received from the mode selecting unit.
    Type: Application
    Filed: December 19, 2006
    Publication date: July 12, 2007
    Inventors: Je-Young Park, Ki-Sang Kang
  • Patent number: 7103493
    Abstract: Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During functional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.
    Type: Grant
    Filed: May 24, 2004
    Date of Patent: September 5, 2006
    Assignee: Samsung Electronics Co., LTD
    Inventors: Ki-Sang Kang, Tsutomu Akiyama, Je-Young Park
  • Publication number: 20050043912
    Abstract: Provided are a memory device testing apparatus and method of operating such an apparatus that can reduce the time required to test a memory device such as a DRAM. The memory testing apparatus includes a pattern generator, a test head, an address pointer, a selector, a failure memory, a failure bit counter and a controller for coordinating the operation of the various elements. Depending on the signals received from the controller, the pattern generator will generate background pattern(s) or test patterns and address information that are, in turn, output to the memory device under test and the selector. During funtional testing of the memory device, failure data is accumulated in a failure memory and subsequently output to a failure bit counter using address information from the address pointer while the background or test pattern is being written to the memory device.
    Type: Application
    Filed: May 24, 2004
    Publication date: February 24, 2005
    Inventors: Ki-Sang Kang, Tsutomu Akiyama, Je-Young Park