Patents by Inventor Jean Brun

Jean Brun has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190177836
    Abstract: A method for producing a waveguide including a germanium-based core and a cladding is provided, the method including a step of “low temperature” depositing of a shell after forming the core by engraving, such that the deposition temperature is less than 780° C., followed by a step of “high temperature” depositing of a thick encapsulation layer. The shell and the encapsulation layer at least partially form the cladding of the waveguide. Optionally, a step of annealing under hydrogen at a “low temperature”, less than 750° C., precedes the deposition of the shell. These “low temperature” annealing and depositing steps advantageously make it possible to avoid a post-engraving alteration of the free surfaces of the core during the forming of the cladding which is less germanium-rich.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Michel Hartmann, Mickael Brun, Jean-Marc Fedeli, Maryse Fournier
  • Publication number: 20190140176
    Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck ARNAUD, David GALPIN, Stephane ZOLL, Olivier HINSINGER, Laurent FAVENNEC, Jean-Pierre ODDOU, Lucile BROUSSOUS, Philippe BOIVIN, Olivier WEBER, Philippe BRUN, Pierre MORIN
  • Patent number: 10264682
    Abstract: The method for assembling a microelectronic chip device (101) in a fabric (104) comprises the following steps: providing a microelectronic chip device (101) comprising a base (102) and a protruding element (103) rising from a face of the base (102), said protruding element (103) comprising a free end opposite the base (102); inserting into the fabric (104) the chip device (101) by the free end of the protruding element; deforming the protruding element (105) at its free end so as to ensure the securing of the chip device (101) with the fabric (104) by forming a crimping bead (106).
    Type: Grant
    Filed: April 24, 2012
    Date of Patent: April 16, 2019
    Assignees: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, POLE EUROPEEN DE PLASTURGIE
    Inventors: Jean Brun, Delphine Christophe, Lionel Tenchine
  • Publication number: 20180355524
    Abstract: A fabrication method of a sheathed yarn includes the following steps: making a core run axially through a sheathing area; winding a sheathing fibre around the core in the sheathing area; and presenting a microelectronic chip fixed onto the core in the sheathing area. A polymer material is present between the microelectronic chip and the core when the sheathing step is performed. The polymer material creeps during the sheathing step to form a protective coating.
    Type: Application
    Filed: October 10, 2016
    Publication date: December 13, 2018
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean BRUN
  • Publication number: 20180309097
    Abstract: Sealing cell for encapsulating a microelectronic component arranged on a substrate, with a cap, said sealing cell including: a bottom including a receiving zone for the substrate and a peripheral zone surrounding the receiving zone, a side wall formed of an internal face, an external face and an upper face, the upper face being configured to support the cap facing the receiving zone, an opening, arranged in the bottom of the cell, in the side wall, or in the cap, the opening being configured to be connected to a pumping system, in such a way as to be able to place under controlled atmosphere a cavity delimited by the side wall, the bottom and the cap.
    Type: Application
    Filed: April 23, 2018
    Publication date: October 25, 2018
    Inventors: Messaoud Bedjaoui, Jean Brun, Johnny Amiran
  • Patent number: 9953953
    Abstract: Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter.
    Type: Grant
    Filed: January 22, 2013
    Date of Patent: April 24, 2018
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean Brun
  • Patent number: 9888573
    Abstract: The cap (1) is intended to be assembled with at least one chipped element (2), said cap comprising a stack of a plurality of electrically insulating layers (1a) delimiting at least one shoulder (3) forming a part of a first groove (4) for housing a wired element (12). The cap further comprises: at least one electrical bump contact (6) arranged at an assembly surface (7) of the stack intended to be mounted on a face of the chipped element (2); at least one electrical connection terminal (5, 5?) arranged at a wall of the shoulder (3); an electrical link element (8), electrically linking said electrical connection terminal (5) to the electrical bump contact (6).
    Type: Grant
    Filed: September 13, 2013
    Date of Patent: February 6, 2018
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Dominique Vicard, Jean Brun
  • Patent number: 9743517
    Abstract: This process for manufacturing an electrically conductive member for an electronic component comprises the following steps: providing a structure comprising at least one blind hole having a bottom and at least one internal lateral flank connected to said bottom via a base of said lateral flank; forming the member, this forming step comprising a step of growing an electrically conductive material in order to form at least one portion of the member in the blind hole, said growth being faster at the base of the lateral flank of the blind hole than on the rest of said lateral flank, said member when formed comprising a cavity arranged at that end of said member which is located opposite the bottom of the blind hole, said cavity being entirely or partially bordered by a rim.
    Type: Grant
    Filed: November 5, 2014
    Date of Patent: August 22, 2017
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean Brun, Abdelhak Hassaine, Jean-Marie Quemper, Régis Taillefer
  • Publication number: 20150318409
    Abstract: The assembly has a central block that includes a first main face, a second main face and side faces. The second main face is opposite to the first main face, and the side faces connect the first main face to the second main face. The assembly also includes a first cover arranged on the first main face. The first main face and a first external surface of the first cover form a first groove for housing a first wire element, and the first groove extends along an entire length of the first main face. The assembly further includes a second cover arranged on the second main face. The second main face and a second external surface of the second cover form a second groove for housing a second wire element, and the second groove extends along an entire length of the second main face.
    Type: Application
    Filed: July 14, 2015
    Publication date: November 5, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Dominique VICARD, Jean BRUN, Pierre PERICHON
  • Patent number: 9179586
    Abstract: A substrate provided with an electrically conducting wire coated with an electrically insulating material is impregnated with a polymerizable material. A reception area for a chip is formed on a surface of the substrate by means of deformation. The housing area is stiffened using the polymerizable material. The chip is disposed in the reception area and an electrical connection area of the chip is connected electrically to the electrically conducting wire of the substrate.
    Type: Grant
    Filed: July 5, 2011
    Date of Patent: November 3, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean Brun
  • Patent number: 9112079
    Abstract: The photovoltaic cell has a block that includes at least one semiconductor substrate in which is formed at least one photovoltaic junction that is connected to a first electrical contact element of a first pole and to a second electrical contact element of a second pole. The cell includes a first transparent cover that is placed on a first surface of the block and defines with the block of the cell a first recess groove of a first electrically conductive wire element.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: August 18, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Dominique Vicard, Jean Brun, Pierre Perichon
  • Publication number: 20150230336
    Abstract: The cap (1) is intended to be assembled with at least one chipped element (2), said cap comprising a stack of a plurality of electrically insulating layers (1a) delimiting at least one shoulder (3) forming a part of a first groove (4) for housing a wired element (12). The cap further comprises: at least one electrical bump contact (6) arranged at an assembly surface (7) of the stack intended to be mounted on a face of the chipped element (2); at least one electrical connection terminal (5, 5?) arranged at a wall of the shoulder (3); an electrical link element (8), electrically linking said electrical connection terminal (5) to the electrical bump contact (6).
    Type: Application
    Filed: September 13, 2013
    Publication date: August 13, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Dominique Vicard, Jean Brun
  • Patent number: 9093289
    Abstract: A method for assembling a device on two substantially parallel taut threads. The device includes an electronic chip and two substantially parallel grooves open on opposite sides of the device. The distance separating the grooves corresponds to the distance separating the threads. The device presents a penetrating shape along an axis perpendicular to the plane of the grooves, having a base at the level of the grooves and an apex of smaller size than the distance separating the threads. The method includes the steps consisting in placing the apex of the device between the two threads; in moving the device between the two threads resulting in the threads being separated from one another by the penetrating shape of the device; and in continuing movement of the device until the threads penetrate into the grooves reverting to their initial separation distance.
    Type: Grant
    Filed: February 2, 2011
    Date of Patent: July 28, 2015
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Dominique Vicard, Jean Brun
  • Publication number: 20150131251
    Abstract: This process for manufacturing an electrically conductive member for an electronic component comprises the following steps: providing a structure comprising at least one blind hole having a bottom and at least one internal lateral flank connected to said bottom via a base of said lateral flank; forming the member, this forming step comprising a step of growing an electrically conductive material in order to form at least one portion of the member in the blind hole, said growth being faster at the base of the lateral flank of the blind hole than on the rest of said lateral flank, said member when formed comprising a cavity arranged at that end of said member which is located opposite the bottom of the blind hole, said cavity being entirely or partially bordered by a rim.
    Type: Application
    Filed: November 5, 2014
    Publication date: May 14, 2015
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean Brun, Abdelhak Hassaine, Jean-Marie Quemper, Régis Taillefer
  • Publication number: 20150024589
    Abstract: Method for assembling includes: providing a system to transfer wire element from wire element supply device to wire element storage device; stretching wire element between supply and storage devices by tensioning; providing an individualized reservoir and separated chip elements, each including a connection terminal including a top with free access facing in which chip element is not present; transporting the chip element from reservoir to an assembly area between supply and storage devices in which wire element is tightly stretched in assembly area; fixing electrically conducting wire element to chip element connection terminal in assembly area; and adding electrically insulating material on chip element after latter has been fixed to wire element forming a cover, the addition of material being performed on surface of chip element including connection terminal fixed to wire element to cover at least the connection terminal and portion of wire element at fixing point of latter.
    Type: Application
    Filed: January 22, 2013
    Publication date: January 22, 2015
    Inventor: Jean Brun
  • Publication number: 20140313743
    Abstract: The method for assembling a microelectronic chip device (101) in a fabric (104) comprises the following steps: providing a microelectronic chip device (101) comprising a base (102) and a protruding element (103) rising from a face of the base (102), said protruding element (103) comprising a free end opposite the base (102); inserting into the fabric (104) the chip device (101) by the free end of the protruding element; deforming the protruding element (105) at its free end so as to ensure the securing of the chip device (101) with the fabric (104) by forming a crimping bead (106).
    Type: Application
    Filed: April 24, 2012
    Publication date: October 23, 2014
    Applicants: Pole Europeen de Plasturgie, Commissariat a L'energie atomique et aux energies Alternatives
    Inventors: Jean Brun, Delphine Christophe, Lionel Tenchine
  • Patent number: 8860200
    Abstract: This invention relates to a stacked electronic device composed of stacked electronic components (120, 130) distributed on one or several added-on levels (N2, N3) each added on the preceding level starting from a base level (N1) possibly containing at least one electronic component (110). At least one electrolytic connection pad of a first type (10.1) on an add-on level (N2) directly connects a conducting element (c1) placed on one face of an electronic component (120) on an add-on level (N2) to a conducting element (z1) placed on an opposite face of a neighboring level (N1) while at least one electrolytic connection pad of a second type (20.1) on the add-on level (N2) passes through a coating layer (220) coating the sides of the electronic component (120) on the add-on level (N2) and directly electrically connects two conducting elements (z1, z2) located on each side of said coating layer (220).
    Type: Grant
    Filed: June 2, 2009
    Date of Patent: October 14, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Jean Brun
  • Patent number: 8814054
    Abstract: A method for forming a sheathed wire includes the steps of: axially advancing a core through a sheathing zone; wrapping a sheathing fiber around the core in the sheathing zone; and providing, in the sheathing zone, a series of microelectronic chip elements each provided with a wire section, in such a way that the sheathing fiber that wraps around the core also wraps around a chip element and the wire section thereof to form a sheathed wire incorporating spaced-apart chip elements.
    Type: Grant
    Filed: June 23, 2011
    Date of Patent: August 26, 2014
    Assignee: Commissariat a l'Energie Atomique et Aux Energies Alternatives
    Inventors: Jean Brun, Laurent Lancon, Dominique Vicard
  • Patent number: 8782880
    Abstract: An apparatus for assembling chip devices on a wire, each chip device comprising two substantially parallel lateral walls, and a groove in one of the lateral walls for receiving said wire. The apparatus includes a pinching device having two opposing surfaces, the distance between the opposing surfaces being substantially constant and substantially equal to the distance between the two lateral walls of a chip device. A wire feeder is adapted to continuously feed the wire in contact with one of the opposing surfaces of the pinching device. A chip device feeder is adapted to drive chip devices, one at a time, between the opposing surfaces, with their grooves turned towards the wire. The pinching device may comprise two cylindrical rollers having rotation axes substantially perpendicular to the wire, the opposing surfaces being formed by respective surfaces of the rollers.
    Type: Grant
    Filed: May 25, 2011
    Date of Patent: July 22, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Dominique Vicard, Jean Brun
  • Patent number: 8723312
    Abstract: The assembly comprises at least one microelectronic chip having two parallel main surfaces and lateral surfaces, at least one of the lateral faces comprising a longitudinal groove housing a wire element having an axis parallel to the longitudinal axis of the groove. The groove is delineated by at least two side walls. The wire element is secured to the chip at the level of a clamping area between at least one bump arranged on one of the side walls, and the side wall of the groove opposite said bump. The clamping area has a smaller height than the diameter of the wire element and a free area is arranged laterally to the bump along the longitudinal axis of the groove. The free area has a height, corresponding to the distance separating the two side walls, that is greater than the diameter of the wire element.
    Type: Grant
    Filed: October 21, 2008
    Date of Patent: May 13, 2014
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventors: Jean Brun, Dominique Vicard, Sophie Verrun