Patents by Inventor Jean-Didier Allegrucci

Jean-Didier Allegrucci has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230353339
    Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
    Type: Application
    Filed: May 2, 2023
    Publication date: November 2, 2023
    Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
  • Patent number: 11683149
    Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
    Type: Grant
    Filed: September 10, 2021
    Date of Patent: June 20, 2023
    Assignee: Apple Inc.
    Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
  • Publication number: 20220085969
    Abstract: A method and apparatus for synchronizing a timebase is disclosed. A timebase management circuit includes limit circuitry, in a first clock domain, which generates, based on a global timebase, an initial timebase limit. The timebase management circuit includes, in a second clock domain, adjustment circuitry that generates an adjusted timebase limit based on the initial timebase limit. A storage circuit in the second clock domain stores a local timebase. Update circuitry, coupled to an output of the storage circuit, generates an updated local timebase using a clock signal in the second clock domain, wherein the updated local timebase is subject to the adjusted timebase limit.
    Type: Application
    Filed: September 10, 2021
    Publication date: March 17, 2022
    Inventors: Christopher D. Finan, Alexander Ukanwa, Charles F. Dominguez, Jean-Didier Allegrucci, Jeffrey J. Irwin, Kalpana Bansal, Michael Bekerman, Remi Clavel
  • Patent number: 9647653
    Abstract: An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.
    Type: Grant
    Filed: June 4, 2015
    Date of Patent: May 9, 2017
    Assignee: Apple Inc.
    Inventors: Shu-Yi Yu, Jean-Didier Allegrucci, Timothy Paaske, Deniz Balkan
  • Publication number: 20160359476
    Abstract: An apparatus may include first and second clock monitors. The first clock monitor may be configured to receive a first clock signal and assert a first signal if the frequency of the first clock signal is greater than a first upper threshold and assert a second signal if the frequency of the first clock signal is less than a first lower threshold. The second clock monitor may be configured to receive a second clock signal with a frequency higher than that of the first clock signal. The second clock monitor may be configured to compare the second clock signal, dependent upon the first clock signal, to second upper and lower thresholds and assert a third signal if the frequency of the second clock signal is greater than the second upper threshold and assert a fourth signal if the frequency is less than the second lower threshold.
    Type: Application
    Filed: June 4, 2015
    Publication date: December 8, 2016
    Inventors: Shu-Yi Yu, Jean-Didier Allegrucci, Timothy Paaske, Deniz Balkan
  • Patent number: 8692755
    Abstract: Embodiments of a system that includes one or more integrated circuits are described. During operation, the system transforms the video image from an initial brightness domain to a linear brightness domain, which includes a range of brightness values corresponding to substantially equidistant adjacent radiant-power values in a displayed video image. In this linear brightness domain, the system may determine an intensity setting of the light source based on at least a portion of the transformed video image, such as the portion of the transformed video image that includes spatially varying visual information in the video image. Moreover, the system may modify the transformed video image so that a product of the intensity setting and a transmittance associated with the modified video image approximately equals a product of a previous intensity setting and a transmittance associated with the video image. For example, the modification may include changing brightness values in the transformed video image.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: April 8, 2014
    Assignee: Apple Inc.
    Inventors: Ulrich T. Barnhoefer, Wei H. Yao, Wei Chen, Barry J. Corlett, Jean-Didier Allegrucci
  • Patent number: 8487948
    Abstract: A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations.
    Type: Grant
    Filed: December 21, 2011
    Date of Patent: July 16, 2013
    Assignee: Vivante Corporation
    Inventors: Mike M. Kai, Jean-Didier Allegrucci, Anthony Ya-Nai Tai
  • Publication number: 20130002651
    Abstract: A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations.
    Type: Application
    Filed: December 21, 2011
    Publication date: January 3, 2013
    Applicant: Vivante Corporation
    Inventors: Mike M. Cai, Jean-Didier Allegrucci, Anthony Ya-Nai Tai
  • Patent number: 8207980
    Abstract: A graphic processing system to compute a texture coordinate. An embodiment of the graphic processing system includes a memory device, a texture coordinate generator, and a display device. The memory device is configured to store a plurality of texture maps. The texture coordinate generator is coupled to the memory device. The texture coordinate generator is configured to compute a final texture coordinate using an arithmetic operation exclusive of a division operation. The display device is coupled to the texture coordinate generator. The display device is configured to display a representation of one of the plurality of texture maps according to the final texture coordinate. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than division.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: June 26, 2012
    Assignee: Vivante Corporation
    Inventors: Mike M. Cai, Anthony Ya-Nai Tai, Jean-Didier Allegrucci
  • Patent number: 8120377
    Abstract: Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.
    Type: Grant
    Filed: June 26, 2009
    Date of Patent: February 21, 2012
    Assignee: Apple Inc.
    Inventors: Jianlin Yu, Michael Frank, Erik P. Machnicki, Jerrold V. Hauck, Jean-Didier Allegrucci, Santiago Fernandez-Gomez
  • Patent number: 8106918
    Abstract: A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations.
    Type: Grant
    Filed: May 1, 2007
    Date of Patent: January 31, 2012
    Assignee: Vivante Corporation
    Inventors: Mike M. Cai, Jean-Didier Allegrucci, Anthony Ya-Nai Tai
  • Publication number: 20120002110
    Abstract: Embodiments of a system that includes one or more integrated circuits are described. During operation, the system receives a video image, that when displayed, includes a picture portion, a non-picture portion, and a subtitle which is superimposed on at least a subset of the non-picture portion, where the non-picture portion has an initial brightness value. Then, the system scales the brightness of pixels corresponding to a remainder of the non-picture portion of the video image to have a new brightness value that is greater than the initial brightness value to reduce user-perceived changes in the video image associated with backlighting of a display that displays the video image, where the remainder of the non-picture portion excludes the subset of the non-picture portion.
    Type: Application
    Filed: September 12, 2011
    Publication date: January 5, 2012
    Applicant: APPLE INC.
    Inventors: Ulrich T. Barnhoefer, Wei H. Yao, Wei Chen, Barry J. Corlett, Jean-Didier Allegrucci
  • Patent number: 8035666
    Abstract: Embodiments of a system that includes one or more integrated circuits are described. During operation, the system receives a video image, that when displayed, includes a picture portion, a non-picture portion, and a subtitle which is superimposed on at least a subset of the non-picture portion, where the non-picture portion has an initial brightness value. Then, the system scales the brightness of pixels corresponding to a remainder of the non-picture portion of the video image to have a new brightness value that is greater than the initial brightness value to reduce user-perceived changes in the video image associated with backlighting of a display that displays the video image, where the remainder of the non-picture portion excludes the subset of the non-picture portion.
    Type: Grant
    Filed: June 24, 2008
    Date of Patent: October 11, 2011
    Assignee: Apple Inc.
    Inventors: Ulrich T. Barnhoefer, Wei H. Yao, Wei Chen, Barry J. Corlett, Jean-Didier Allegrucci
  • Publication number: 20100333055
    Abstract: Methods for enabling a secure test mode, and integrated circuits (IC's) implementing the same are disclosed. An IC may include a secure functional unit that is protected from access from test access circuitry during normal operation. The secure functional unit may be rendered inaccessible the test access circuitry of the IC following a completion of a test that includes testing of the secure functional unit. An embodiment of an IC that includes circuitry to delay entry into a test mode while a chip-level reset is performed is also contemplated. Entry into the test mode may be delayed until all circuitry of the IC has been fully reset in order to clear stored information.
    Type: Application
    Filed: June 26, 2009
    Publication date: December 30, 2010
    Inventors: Jianlin Yu, Michael Frank, Erik P. Machnicki, Jerrold V. Hauck, Jean-Didier Allegrucci, Santiago Fernandez-Gomez
  • Publication number: 20090002555
    Abstract: Embodiments of a system that includes one or more integrated circuits are described. During operation, the system transforms the video image from an initial brightness domain to a linear brightness domain, which includes a range of brightness values corresponding to substantially equidistant adjacent radiant-power values in a displayed video image. In this linear brightness domain, the system may determine an intensity setting of the light source based on at least a portion of the transformed video image, such as the portion of the transformed video image that includes spatially varying visual information in the video image. Moreover, the system may modify the transformed video image so that a product of the intensity setting and a transmittance associated with the modified video image approximately equals a product of a previous intensity setting and a transmittance associated with the video image. For example, the modification may include changing brightness values in the transformed video image.
    Type: Application
    Filed: June 24, 2008
    Publication date: January 1, 2009
    Applicant: APPLE INC.
    Inventors: Ulrich T. Barnhoefer, Wei H. Yao, Wei Chen, Barry J. Corlett, Jean-Didier Allegrucci
  • Publication number: 20090002565
    Abstract: Embodiments of a system that includes one or more integrated circuits are described. During operation, the system receives a video image, that when displayed, includes a picture portion, a non-picture portion, and a subtitle which is superimposed on at least a subset of the non-picture portion, where the non-picture portion has an initial brightness value. Then, the system scales the brightness of pixels corresponding to a remainder of the non-picture portion of the video image to have a new brightness value that is greater than the initial brightness value to reduce user-perceived changes in the video image associated with backlighting of a display that displays the video image, where the remainder of the non-picture portion excludes the subset of the non-picture portion.
    Type: Application
    Filed: June 24, 2008
    Publication date: January 1, 2009
    Applicant: Apple Inc.
    Inventors: Ulrich T. Barnhoefer, Wei H. Yao, Wei Chen, Barry J. Corlett, Jean-Didier Allegrucci
  • Publication number: 20080273043
    Abstract: A graphic processing system to compute a texture coordinate. An embodiment of the graphic processing system includes a memory device, a texture coordinate generator, and a display device. The memory device is configured to store a plurality of texture maps. The texture coordinate generator is coupled to the memory device. The texture coordinate generator is configured to compute a final texture coordinate using an arithmetic operation exclusive of a division operation. The display device is coupled to the texture coordinate generator. The display device is configured to display a representation of one of the plurality of texture maps according to the final texture coordinate. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than division.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 6, 2008
    Applicant: GiQuila Corporation
    Inventors: Anthony Ya-Nai Tai, Jean-Didier Allegrucci
  • Publication number: 20080273042
    Abstract: A graphic processing system to compute a texture level of detail. An embodiment of the graphic processing system includes a memory device, a driver, and level of detail computation logic. The memory device is configured to implement a first lookup table. The first lookup table is configured to provide a first level of detail component. The driver is configured to calculate a log value of a second level of detail component. The level of detail computation logic is coupled to the memory device and the driver. The level of detail computation logic is configured to compute a level of detail for a texture mapping operation based on the first level of detail component from the lookup table and the second level of detail component from the driver. Embodiments of the graphic processing system facilitate a simple hardware implementation using operations other than multiplication, square, and square root operations.
    Type: Application
    Filed: May 1, 2007
    Publication date: November 6, 2008
    Inventors: Mike M. Cai, Jean-Didier Allegrucci, Anthony Ya-Nai Tai
  • Patent number: 7139848
    Abstract: According to one embodiment a system is described. The system includes a direct memory access (DMA) controller and an input/output (I/O) device coupled to the DMA controller. The DMA controller is adaptable to operate in a normal mode and a descriptor mode.
    Type: Grant
    Filed: December 8, 2000
    Date of Patent: November 21, 2006
    Assignee: Xilinx, Inc.
    Inventors: James Murray, Jean-Didier Allegrucci
  • Patent number: 6985980
    Abstract: A scheme for freezing the clock of a CSOC to obtain a static view of the hardware for debugging purposes. A breakpoint unit is programmed to break on specific conditions or sequence of events. The breakpoint unit monitors the bus. Upon the occurrence of the programmed event the breakpoint unit generates a clock freeze signal. The clock freeze event signal is input to the bus arbiter which causes the bus arbiter to stop granting access to the bus to any bus master except the debug port. The bus arbiter checks for pending transactions on the bus and monitors the completion of any pending transactions. This ensures that the system will not be frozen while in a wait state which would render the bus inoperable. Once all pending transactions are complete, the bus arbiter generates a qualified clock freeze signal to the CSL clock thereby freezing the system for debugging.
    Type: Grant
    Filed: November 3, 2000
    Date of Patent: January 10, 2006
    Assignee: Xilinx, Inc.
    Inventor: Jean-Didier Allegrucci