Abstract: This invention relates to methods and kits for use in vaccination against dengue virus infection.

Abstract: The invention relates to a method for inducing protection against the 4 serotypes of dengue fever in a patient, comprising: (a) the administration of a monovalent vaccine comprising a vaccinal virus of a first serotype of dengue fever, and (b) the administration of a tetravalent vaccine comprising vaccinal viruses of the four serotypes of dengue fever, in which administration (b) is made between at least 30 days and not more than 12 months following the first administration (a).

Abstract: The invention relates to a method for inducing a protection against the 4 dengue serotypes in a patient, comprising (a) a first series of administrations (i) of a dose of a vaccinal dengue virus of a first serotype and of a dose of a vaccinal dengue virus of a second serotype, and (ii) of a dose of a vaccinal dengue virus of a third serotype and of a dose of a vaccinal dengue virus of a fourth serotype, and (b) a second series of administrations of doses (i) and (ii), in which the doses (i) and (ii) are administered simultaneously at separate anatomical sites, and in which the second series (b) is implemented at least 30 days to at most 12 months after the first series (a).

Abstract: The invention relates to a method for inducing a homologous protection against the 4 dengue serotypes in a patient, comprising the sequential administration, to said patient, (i) of a dose of a vaccinal dengue virus of a first serotype and of a dose of a vaccinal dengue virus of a second serotype, and (ii) of a dose of a vaccinal dengue virus of a third serotype and of a dose of a vaccinal dengue virus of a fourth serotype, in which the vaccinal dengue viruses (ii) are administered at least 30 days and at most 1 year after administration of the vaccinal viruses (i).

Abstract: The invention relates to live attenuated VDV2 (VERO-Derived Vaccine Dengue serotype 2) strains which have been derived from the wild-type dengue-2 strain 16681 by passaging on PDK and Vero cells. The invention further relates to a vaccine composition which comprises a VDV2 strain.

Abstract: The invention relates to live attenuated VDV1 (VERO-Derived Dengue serotype 1 viruse) strains which have been derived from the wild-type dengue-1 strain 16007 by passaging on PDK and sanitization on Vero cells. The invention further relates to a vaccine composition which comprises a VDV1 strain.

Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Abstract: A microcomputer system memory architecture and method allows the system memory to provide data access at high speeds in a burst mode. The architecture and method utilizes a system memory controller capable of performing the addressing of the system memory. The microprocessor and the system memory communicate via a high speed host bus. The system memory is comprised of multiple 64-bit system memory buses to permit high speed data transfer to the microprocessor in a burst mode without the need for an external cache.

Abstract: A microcomputer architecture and method allows for high processing speeds. A microprocessor constitutes the central processing unit. The microprocessor comprises an on-chip cache memory and is capable of reading data in a burst mode. The central processing unit and the system memory communicate by way of a high speed host bus. The system memory is comprised of multiple buses and is capable of delivering data to the microprocessor in a burst mode at high speeds. A memory controller addresses data locations within the system memory upon receipt of a first host address from the microprocessor. Accordingly, the microprocessor can access data in the system memory at an extremely fast rate when operating in a burst mode. High speed processing is accomplished without the need for an external cache.