Patents by Inventor Jean Lasseuguette
Jean Lasseuguette has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 10173892Abstract: This application relates to an integrated circuit die (200) comprising a MEMS transducer structure (101) integrated with associated electronic circuitry (102). The electronic circuitry comprises a plurality of transistors and associated interconnections and is formed in a first area (103) of the die from a first plurality (104) of layers, e.g. formed by CMOS metal (107) and dielectric (108) layers and possibly doped areas (106) of substrate (105). The MEMS transducer structure is formed in a second area (111) of the die and is formed, at least partly, from a second plurality (112) of layers which are separate to the first plurality of layers. At least one filter circuit (201) is formed from said second plurality of layers overlying the plurality of transistors of the electronic circuitry (102).Type: GrantFiled: July 30, 2015Date of Patent: January 8, 2019Assignee: Cirrus Logic, Inc.Inventors: James Deas, Jean Lasseuguette, John Pennock, Mark Hesketh
-
Publication number: 20170217757Abstract: This application relates to an integrated circuit die (200) comprising a MEMS transducer structure (101) integrated with associated electronic circuitry (102). The electronic circuitry comprises a plurality of transistors and associated interconnections and is formed in a first area (103) of the die from a first plurality (104) of layers, e.g. formed by CMOS metal (107) and dielectric (108) layers and possibly doped areas (106) of substrate (105). The MEMS transducer structure is formed in a second area (111) of the die and is formed, at least partly, from a second plurality (112) of layers which are separate to the first plurality of layers. At least one filter circuit (201) is formed from said second plurality of layers overlying the plurality of transistors of the electronic circuitry (102).Type: ApplicationFiled: July 30, 2015Publication date: August 3, 2017Applicant: Cirrus Logic International Semiconductor Ltd.Inventors: James DEAS, Jean LASSEUGUETTE, John PENNOCK, Mark HESKETH
-
Patent number: 9397690Abstract: An apparatus for sensing current of a vehicle battery employs an extended counting analog-to-digital conversion process (212) to a chopped and amplified voltage appearing across a low ohmic shunt resistor (203) placed between the negative pole of the vehicle's battery and the chassis ground of the vehicle. Gain adjustment control of a programmable gain amplifier (209) by matching the gain to the dynamic range of the ADC (212) permits a high dynamic signal sensing.Type: GrantFiled: March 21, 2013Date of Patent: July 19, 2016Assignee: Freescale Semiconductor, Inc.Inventors: Jean Lasseuguette, Jérôme Casters, Stéphane Ollitrault, Thierry Robin, Olivier Tico
-
Publication number: 20150381198Abstract: An apparatus for sensing current of a vehicle battery employs an extended counting analogue-to-digital conversion process to a chopped and amplified voltage appearing across a low ohmic shunt resistor placed between the negative pole of the vehicle's battery and the chassis ground of the vehicle. Gain adjustment control of a programmable gain amplifier by matching the gain to the dynamic range of the ADC permits a high dynamic signal sensing.Type: ApplicationFiled: March 21, 2013Publication date: December 31, 2015Applicant: FREESCALE SEMICONDUCTOR, INC.Inventors: JEAN LASSEUGUETTE, JÉRÔME CASTERS, STÉPHANE OLLITRAULT, THIERRY ROBIN, OLIVIER TICO
-
Publication number: 20140285175Abstract: A reference voltage generating circuit comprising a first bandgap voltage source arranged to output a first bandgap voltage exhibiting a first type deviation in response to a strain applied at die level in a given direction; a second bandgap voltage source arranged to output a second bandgap voltage exhibiting a second type deviation in response to a strain applied at die level in the given direction, said second type deviation being opposite to the first type deviation of the first bandgap voltage; and an adding circuit arranged to add the first bandgap voltage and the second bandgap voltage, and to output a temperature drift and strain drift compensated reference voltage.Type: ApplicationFiled: November 4, 2011Publication date: September 25, 2014Applicant: FREESCALE SEMICONDUCTOR, INC.Inventor: Jean Lasseuguette
-
Patent number: 7881138Abstract: A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal and the reference signal. The comparator further includes a first output stage for generating a first comparator output signal by comparing the output signal and the bias signal. The comparator further includes a second output stage for generating a second comparator output signal by comparing the reference signal and the bias signal.Type: GrantFiled: July 10, 2006Date of Patent: February 1, 2011Assignee: Freescale Semiconductor, Inc.Inventors: Brad Garni, Thomas Andre, Jean Lasseuguette
-
Publication number: 20090290443Abstract: A memory has a pre-amplifier for generating an output signal and a reference signal. The memory includes a comparator for comparing the output signal to the reference signal. The comparator includes a bias stage for generating a bias signal, wherein the bias signal is an average of the output signal and the reference signal. The comparator further includes a first output stage for generating a first comparator output signal by comparing the output signal and the bias signal. The comparator further includes a second output stage for generating a second comparator output signal by comparing the reference signal and the bias signal.Type: ApplicationFiled: July 10, 2006Publication date: November 26, 2009Applicant: Freescale Semiconductor, IncInventors: Brad Garni, Thomas Andre, Jean Lasseuguette
-
Patent number: 7545686Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.Type: GrantFiled: March 17, 2005Date of Patent: June 9, 2009Assignee: STMicroelectronics S.A.Inventors: Jean Lasseuguette, Cyrille Dray, Sébastien Barasinski
-
Patent number: 7466595Abstract: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.Type: GrantFiled: February 19, 2008Date of Patent: December 16, 2008Assignee: STMicroelectronics S.A.Inventor: Jean Lasseuguette
-
Publication number: 20080137430Abstract: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.Type: ApplicationFiled: February 19, 2008Publication date: June 12, 2008Applicant: STMicroelectronics S.A.Inventor: Jean Lasseuguette
-
Patent number: 7372728Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: GrantFiled: April 23, 2007Date of Patent: May 13, 2008Assignees: STMicroelectronics, Inc., STMicroelectronics S.A.Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel
-
Patent number: 7289355Abstract: A memory cell of the SRAM type is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 or 26) of a first type and a transistor (25 or 27) of a second type. The concentration of carriers in the conduction channel of the transistor (24) of the first type of one of the inverters (20) is different from the concentration of carriers in the conduction channel of the transistor (26) of the first type of the other inverter (21) so that the inverters have different threshold voltages.Type: GrantFiled: October 25, 2005Date of Patent: October 30, 2007Assignee: STMicroelectronics SAInventors: Philippe Candelier, Jean Lasseuguette, Richard Fournel
-
Publication number: 20070217265Abstract: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.Type: ApplicationFiled: February 1, 2007Publication date: September 20, 2007Applicant: STMicroelectronics S.A.Inventor: Jean Lasseuguette
-
Publication number: 20070189066Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: ApplicationFiled: April 23, 2007Publication date: August 16, 2007Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sebastien Barasinski, Richard Fournel
-
Patent number: 7209383Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: GrantFiled: June 23, 2005Date of Patent: April 24, 2007Assignee: STMicroelectronics, Inc.Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sébastien Barasinski, Richard Fournel
-
Patent number: 7139212Abstract: A memory device includes at least one segmented writing line formed by at least one writing segment. A programming circuit is controlled by a line address circuit in a writing mode of the memory device to program at least one memory cell coupled to the segmented writing line. A reading bit line is connected to a reading circuit for reading the contents of the cell in a reading mode of the memory device. The reading bit line cooperates in writing mode with the line address circuit to control the programming circuit of the segmented writing line.Type: GrantFiled: June 14, 2005Date of Patent: November 21, 2006Assignee: STMicroelectronics S.A.Inventors: Cyrille Dray, Sébastien Barasinski, Jean Lasseuguette, Christophe Frey, Richard Fournel
-
Publication number: 20060171227Abstract: The invention relates to a circuit for reading a cell of a bit line, including first and second transistors for controlling the bit line and a reference line, respectively, a reference transistor connected to the second control transistor and a write transistor of the reference current connected to the first control transistor, for comparing the current of the bit line and the reference current, characterized in that a first intermediate transistor is connected to the write transistor parallel to the first control transistor, and in that a second intermediate transistor is connected between the gate and the drain of the reference transistor parallel to the second control transistor, and polarization transistors are connected in series, respectively, to the intermediate transistors so as to superimpose a current over the reference current.Type: ApplicationFiled: November 17, 2005Publication date: August 3, 2006Applicant: STMicroelectronics S.A.Inventor: Jean Lasseuguette
-
Publication number: 20060139990Abstract: A memory cell of the SRAM type Is provided that is capable of storing one datum in a non-volatile manner. The memory cell includes two inverters (20 and 21) configured as a flip-flop for storing one bit. Each inverter includes a transistor (24 or 26) of a first type and a transistor (25 or 27) of a second type. The concentration of carriers in the conduction channel of the transistor (24) of the first type of one of the inverters (20) is different from the concentration of carriers in the conduction channel of the transistor (26) of the first type of the other inverter (21) so that the inverters have different threshold voltages.Type: ApplicationFiled: October 25, 2005Publication date: June 29, 2006Applicant: STMICROELECTRONICS SAInventors: Philippe Candelier, Jean Lasseuguette, Richard Fournel
-
Publication number: 20060050585Abstract: The invention relates to a device for setting up a write current on at least one write conducting line in an MRAM type integrated circuit memory, including a current mirror composed of a first stage acting as the reference regulated cascode stage receiving all or part of the write current on its input and a second stage acting as the copy regulated cascode stage copying the write current onto the write line.Type: ApplicationFiled: March 17, 2005Publication date: March 9, 2006Applicant: STMicroelectronics S.A.Inventors: Jean Lasseuguette, Cyrille Dray, Sebastien Barasinski
-
Publication number: 20050281080Abstract: A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row.Type: ApplicationFiled: June 23, 2005Publication date: December 22, 2005Inventors: Cyrille Dray, Christophe Frey, Jean Lasseuguette, Sebastien Barasinski, Richard Fournel