Abstract: For certain operations executed in a multiprocessor system, the processors communicate with one another by exchanging requests and acknowledgements. To improve performance, the invention proposes a method by which the operations which require sending of multiple requests proceed without taking into account the reception of the acknowledgements. The total number of requests required is calculated and the number of acknowledgements received is counted. The end of the operation is conditioned by the equality of these two numbers. The invention also relates to a system for employing the method, and to the application of the method to dispatching.

Abstract: A microprogram controlled operator device is described which processes bytes each of which is comprised of an equal number of binary-coded decimal figures. The device comprises first and second byte stores each of a multi-byte capacity, a logical and arithmetical operator circuit having inputs connected to read-out outputs of said stores and having an output to a buffer register and code handling organization, preferably further enabling "raw" byte inputting. An output of the code handling organization is connected to an input of a byte code processing arrangement which includes a multiplexer circuit having outputs to write-in inputs of the first and second stores and having further inputs connected to external data supplying means and to read-out outputs from the said stores. The organization further has an output to the external equipment wherein said device is connected.

Abstract: A field selection data operating device consists of three cascade connected circuits: a field selector and shifter circuit, an arithmetical and logical operator circuit and a bit shifter and concatenator circuit. The selector and shifter circuit is controlled by a field length code, a shift value code and a first field bit rank code. It comprises two stages of multiplexing members. The first stage ensures, in circular permutation, a shift of the bytes of an applied data word so as to place the byte containing the bit of the first field bit rank code at the place in the word pointed by the shift value code and the second stage completes the shift to the said bit in the byte and generates an output mask according to the field length code. The mask is also applied to concatenation control inputs of the bit shifter and concatenator circuit.

Abstract: An addressing device is described for a control store comprised of a read-only storage portion and a read-write storage portion, each divided in addressable microprogram sectors and both accessible through a common address register and accessing to a common read-out register. Said control store is a part of a multimicroprogrammed unit further comprising a logical unit, a status register for said logical unit and an automatic store address forming organization operating on data supplied from the common read-out register and the logical unit. When a microprogram stored in a sector of the read-write storage portion must be substituted for a microprogram stored in a sector of the read-only storage portion, the logical unit forces into the status register, a pointer code and the sector addresses of the concerned read-only and read-write storage portions.

Abstract: A supervising device is described for detecting errors in an automatic progression of the addresses of words which must be sequentially read out from a store under the control of a command logic forming the starting address from an operation code and thereafter incrementing the address by combining a portion of each read-out word with other data. Said device comprises a code comparator the output of which is activated when a code of a restricted number of bits derived from the operation code and a code of the same number of bits derived from a read out word disagree except when this second code presents a particular configuration of bits as, for instance an all identical binary value bit configuration.