Patents by Inventor Jean-Marc Mourant

Jean-Marc Mourant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10790804
    Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
    Type: Grant
    Filed: April 24, 2016
    Date of Patent: September 29, 2020
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Shawn Bawell, Jean-Marc Mourant, Feng-Jung Huang
  • Publication number: 20190372823
    Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.
    Type: Application
    Filed: August 16, 2019
    Publication date: December 5, 2019
    Inventors: Chuying MAO, Ran LI, Jean-Marc MOURANT
  • Patent number: 10389572
    Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.
    Type: Grant
    Filed: June 23, 2017
    Date of Patent: August 20, 2019
    Assignee: Integrated Device Technology, Inc.
    Inventors: Chuying Mao, Ran Li, Jean-Marc Mourant
  • Patent number: 10320381
    Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: June 11, 2019
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Kathiravan Krishnamurthi, Jean-Marc Mourant, Olivier Hubert, Shawn Bawell
  • Publication number: 20180375711
    Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.
    Type: Application
    Filed: June 23, 2017
    Publication date: December 27, 2018
    Inventors: CHUYING MAO, Ran LI, Jean-Marc MOURANT
  • Patent number: 10103711
    Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.
    Type: Grant
    Filed: June 5, 2014
    Date of Patent: October 16, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Shawn Bawell, Jean-Marc Mourant, Olivier Hubert
  • Patent number: 10103690
    Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.
    Type: Grant
    Filed: July 25, 2016
    Date of Patent: October 16, 2018
    Assignee: INTEGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Naveen Yanduru, Chris Stephens, Jean-Marc Mourant, Chuying Mao
  • Publication number: 20180026583
    Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.
    Type: Application
    Filed: July 25, 2016
    Publication date: January 25, 2018
    Inventors: Naveen Yanduru, Chris Stephens, Jean-Marc Mourant, Chuying Mao
  • Patent number: 9853616
    Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 26, 2017
    Assignee: INTERGRATED DEVICE TECHNOLOGY, INC.
    Inventors: Feng-Jung Huang, Jean-Marc Mourant
  • Publication number: 20160285447
    Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.
    Type: Application
    Filed: March 27, 2015
    Publication date: September 29, 2016
    Inventors: Kathiravan Krishnamurthi, Jean-Marc Mourant, Olivier Hubert, Shawn Bawell
  • Publication number: 20160241216
    Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
    Type: Application
    Filed: April 24, 2016
    Publication date: August 18, 2016
    Inventors: SHAWN BAWELL, Jean-Marc Mourant, Feng-Jung Huang
  • Patent number: 9374078
    Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: June 21, 2016
    Assignee: INTEGRATED DEVICE TECHNOLOGY iNC.
    Inventors: Shawn Bawell, Jean-Marc Mourant, Feng-Jung Huang
  • Publication number: 20150358015
    Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.
    Type: Application
    Filed: June 5, 2014
    Publication date: December 10, 2015
    Inventors: Shawn Bawell, Jean-Marc Mourant, Olivier Hubert
  • Publication number: 20140320207
    Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Inventors: Feng-Jung Huang, Jean-Marc Mourant
  • Patent number: 8704684
    Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
    Type: Grant
    Filed: June 30, 2012
    Date of Patent: April 22, 2014
    Assignee: Integrated Device Technology Inc.
    Inventors: Shawn Bawell, Jean-Marc Mourant, Feng-Jung Huang
  • Publication number: 20140002214
    Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
    Type: Application
    Filed: June 30, 2012
    Publication date: January 2, 2014
    Inventors: Shawn Bawell, Jean-Marc Mourant, Feng-Jung Huang
  • Publication number: 20140002282
    Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.
    Type: Application
    Filed: June 30, 2012
    Publication date: January 2, 2014
    Inventors: Shawn Bawell, Jean-Marc Mourant, Feng-Jung Huang
  • Patent number: 8604879
    Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
    Type: Grant
    Filed: March 30, 2012
    Date of Patent: December 10, 2013
    Assignee: Integrated Device Technology Inc.
    Inventors: Jean-Marc Mourant, Feng-Jung Huang, Ran Li, Chuying Mao
  • Publication number: 20130257537
    Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.
    Type: Application
    Filed: March 30, 2012
    Publication date: October 3, 2013
    Inventors: Jean-Marc Mourant, Feng-Jung Huang, Ran Li, Chuying Mao
  • Patent number: 8456237
    Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.
    Type: Grant
    Filed: July 29, 2011
    Date of Patent: June 4, 2013
    Assignee: Integrated Device Technology, Inc.
    Inventors: Feng-Jung Huang, Jean-Marc Mourant