Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.

Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.

Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.

Abstract: Wide band quadrature signal generation includes a frequency synthesizer generating a LO or 2×LO signal, a polyphase filter coupled to receive the LO signal and generate first in-phase and quadrature LO signals, a 2:1 frequency divider coupled to receive the 2×LO signal and generate second in-phase and quadrature LO signals, and a LO signal selector for selecting either the first or second in-phase LO signals as an output in-phase LO signal and either the first or second quadrature LO signals as an output quadrature LO signal based on an output frequency. In some embodiments, when the output frequency is above a threshold, the first in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals and when the output frequency is at or below the threshold, the second in-phase and quadrature LO signals are selected as the output in-phase and quadrature LO signals.

Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.

Abstract: Systems, methods and instrumentalities are disclosed for Doherty amplifier optimization. Amplifier configurability and control therefore may be integrated. Amplitude alignment, phase alignment, amplifier gate biasing, driver gate biasing and temperature compensation for N paths in Doherty configurations may be integrated, for example, using a programmable LUT storing control bit patterns. Configurability may comprise reconfigurability between asymmetric power split ratios, between symmetric and asymmetric relationships and between classic and inverted phase relationships, permitting path reconfigurability for higher or lower power and leading or lagging phase. Multiple versions providing more or less configurability and/or control range with more or less insertion loss, such as design and production versions, may be pin compatible, e.g., to reduce time and expense for R&D and production transition.

Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.

Abstract: Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: A constant impedance switch dynamically manages switch impedance to eliminate or substantially reduce impedance glitches during switching events by stepping variable impedances through sequences of impedance values. As a result, VSWR may be reduced to or near 1:1, allowing programming and circuitry to be simplified. Switch impedance may be maintained for single and multi-throw switches having variable impedances of any order. Each variable impedance may comprise one or more configurable cells, subcells and elements controlled by thermometer, binary, hybrid or other coding technique.

Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: Hybrid-coding, multi-cell architecture and operating techniques for step devices provide advantages over binary-coded and thermometer-coded step devices by minimizing or avoiding glitches common in the transient response of binary-coded step devices and by minimizing or avoiding significant increases or degradation in one or more of area, package dimensions, pin counts, power consumption, insertion loss and parasitic capacitance common to thermometer-coded step devices having equivalent range and resolution.

Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.

Abstract: An impedance-matched amplifier utilizing a feed-forward linearization technique involving multiple negative feedbacks and distortion compensation without active tail current sources reduces noise, distortion, power consumption and heat dissipation requirements and increases linearity, dynamic range, signal-to-noise-ratio, sensitivity and quality of service. Some differential amplifier embodiments of the invention consume less than 2 mA at 5 Volts or 10 mW power consumption per 1 mW in peak and sustained output IP3 performance above 40 dBm. In contrast, for an input signal frequency of 200 MHz, a 16 dB gain state-of-the-art differential amplifier consumes 100 mA at 5 Volts with a peak output IP3 of 36 dBm while an implementation of a 16 dB gain differential amplifier embodying the invention consumes 77.7 mA at 5 Volts with a peak output IP3 of 46 dBm and sustained at or above 40 dBm over a wide frequency range.

Abstract: Variable feedback architecture and control techniques for variable gain amplifiers (VGAs) concurrently maintain, across a wide range of VGA gain settings, minimal input and output impedance variations, a low noise figure, low rates of change in noise figure, high signal-to-noise ratio (SNR), high quality of service (QoS), low distortion, high and relatively constant output third order intercept point (i.e., IP3 or TOI). Variable feedback counteracts impedance variations caused by gain variations. Compared to conventional high performance VGAs, noise figure is lower (e.g. 3 dB lower at maximum gain and 12 dB lower at minimum gain) and relatively constant, IP3 is higher and relatively constant, small signal third order intermodulation signal (IM3) tone slope is relatively constant and input and output impedances are relatively constant. As gain decreases, the noise figure advantage is nearly dB per dB compared to conventional high performance VGAs.