Patents by Inventor Jean-Marc Waechter

Jean-Marc Waechter has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7648888
    Abstract: The invention relates to a method of splitting apart a substrate of two adjoining wafers defining between them a cleavage plane, by bringing each substrate into a substrate-receiving space; and clamping first and second jaw portions onto each substrate in such a manner as to hold each substrate and urge apart the two wafers of each substrate by co-operation between the shapes of housings in first and second portions of the two jaws, respectively. The invention also relates to a splitting method that includes bringing each substrate into a substrate-reception space; clamping together separator portions onto each substrate so as to split apart the two wafers of each substrate; and clamping the split-apart substrate wafers so as to hold the wafers together. An automated system for processing multiple substrates is also provided.
    Type: Grant
    Filed: January 24, 2006
    Date of Patent: January 19, 2010
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
  • Patent number: 7601606
    Abstract: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.
    Type: Grant
    Filed: September 28, 2006
    Date of Patent: October 13, 2009
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Francois Brunier, Vivien Renauld, Jean Marc Waechter
  • Patent number: 7466907
    Abstract: A device for use in a thermal annealing process for a wafer (T) of material chosen among the semiconductor materials for the purpose of detaching a layer from the wafer at an weakened zone. During annealing, the device applies (1) a basic thermal budget to the wafer, with the basic thermal budget being slightly inferior to the budget necessary to detach the layer, this budget being distributed in an even manner over the weakened zone; and (2) an additional thermal budget is also applied to the wafer locally in a set region of the weakened zone so as to initiate the detachment of the layer in this region.
    Type: Grant
    Filed: May 16, 2006
    Date of Patent: December 16, 2008
    Assignee: S.O.I.Tec Silicon on Insulator Technologies
    Inventors: Walter Schwarzenbach, Jean-Marc Waechter
  • Publication number: 20070020886
    Abstract: The invention provides methods for reducing trap densities at interfaces in a multilayer semiconductor wafer, specifically trap densities between an active layer and an insulating layer under the active layer. The methods comprise exposing wafers to high temperatures in a generally neutral atmosphere that also comprises one or more species that can, or whose ions can, migrate into the wafer down to the interface where reduction of the trap density is desired.
    Type: Application
    Filed: September 28, 2006
    Publication date: January 25, 2007
    Inventors: Francois Brunier, Vivien Renauld, Jean Marc Waechter
  • Publication number: 20060204230
    Abstract: The invention relates to a device for use in a thermal annealing process for a wafer (T) of material chosen among the semiconductor materials for the purpose of detaching a layer from the wafer at an weakened zone, characterized in that during annealing, the device applies (1) a basic thermal budget to the wafer, with the basic thermal budget being slightly inferior to the budget necessary to detach the layer, this budget being distributed in an even manner over the weakened zone; and (2) an additional thermal budget is also applied to the wafer locally in a set region of the weakened zone so as to initiate the detachment of the layer in this region.
    Type: Application
    Filed: May 16, 2006
    Publication date: September 14, 2006
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A., a French company
    Inventors: Walter Schwarzenbach, Jean-Marc Waechter
  • Patent number: 7098148
    Abstract: A method for heat treatment of a semiconductor wafer placed on a support. The method includes subjecting the wafer to a heat treatment with a slow temperature rise from an initial temperature to a treatment ending temperature, and minimizing slip lines that would otherwise result in the wafer from the heat treatment by introducing at least one temperature plateau of constant temperature and of predetermined duration in the heat treatment before reaching the treatment ending temperature. The method reduces the temperature gradients on the wafer to minimize slip lines in the wafer resulting from the heat treatment.
    Type: Grant
    Filed: June 9, 2004
    Date of Patent: August 29, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Walter Schwarzenbach, Jean-Marc Waechter
  • Patent number: 7094668
    Abstract: A device and method for annealing a wafer. The preferred embodiment includes applying a basic thermal budget to a weakened zone of a wafer, substantially evenly over the weakened zone. The basic thermal budget is insufficient to detach a detachment layer from a remainder of the wafer at the weakened zone. An additional thermal budget is applied locally in an initiation region of the weakened zone to initiate the detachment of the detachment layer at the weakened zone.
    Type: Grant
    Filed: November 20, 2003
    Date of Patent: August 22, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Walter Schwarzenbach, Jean-Marc Waechter
  • Publication number: 20060138189
    Abstract: The invention relates to a method of splitting apart a substrate of two adjoining wafers defining between them a cleavage plane, by bringing each substrate into a substrate-receiving space; and clamping first and second jaw portions onto each substrate in such a manner as to hold each substrate and urge apart the two wafers of each substrate by co-operation between the shapes of housings in first and second portions of the two jaws, respectively. The invention also relates to a splitting method that includes bringing each substrate into a substrate-reception space; clamping together separator portions onto each substrate so as to split apart the two wafers of each substrate; and clamping the split-apart substrate wafers so as to hold the wafers together. An automated system for processing multiple substrates is also provided.
    Type: Application
    Filed: January 24, 2006
    Publication date: June 29, 2006
    Applicant: S.O.I.Tec Silicon on Insulator Technologies S.A., a French company
    Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
  • Patent number: 7017570
    Abstract: The invention provides an apparatus for splitting a substrate apart, the substrate comprising two adjoining wafers defining between them a cleavage plane, the apparatus being characterized in that it comprises: means for feeding splitter means with a plurality of substrates disposed in a substrate-storage direction; splitter means for splitting apart wafers of the substrates, the splitter means comprising moving jaws; and means for performing controlled displacement of certain substrate wafers after they have been split apart in a direction that is substantially parallel to the substrate-storage direction, whereby the apparatus is suitable for splitting apart the plurality of substrates. The invention also provides an associated splitting method.
    Type: Grant
    Filed: February 9, 2004
    Date of Patent: March 28, 2006
    Assignee: S.O.I.Tec Silicon on Insulator Technologies S.A.
    Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
  • Publication number: 20040259388
    Abstract: A method for heat treatment of a semiconductor wafer placed on a support. The method includes subjecting the wafer to a heat treatment with a slow temperature rise from an initial temperature to a treatment ending temperature, and minimizing slip lines that would otherwise result in the wafer from the heat treatment by introducing at least one temperature plateau of constant temperature and of predetermined duration in the heat treatment before reaching the treatment ending temperature. The method reduces the temperature gradients on the wafer to minimize slip lines in the wafer resulting from the heat treatment.
    Type: Application
    Filed: June 9, 2004
    Publication date: December 23, 2004
    Inventors: Walter Schwarzenbach, Jean-Marc Waechter
  • Publication number: 20040188487
    Abstract: The invention provides an apparatus for splitting a substrate apart, the substrate comprising two adjoining wafers defining between them a cleavage plane, the apparatus being characterized in that it comprises:
    Type: Application
    Filed: February 9, 2004
    Publication date: September 30, 2004
    Inventors: Thierry Barge, Walter Schwarzenbach, Jean-Marc Waechter, Thuan Truong, Bruno Ghyselen
  • Patent number: 6770144
    Abstract: There is disclosed a high throughput multideposition SACVD reactor that enables the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a semiconductor substrate in the same chamber according to the desired sequence. Such a reactor has a processing chamber which is well adapted to single semiconductor wafer processing. The processing chamber includes an improved susceptor to support the wafer and a specific gas distribution system adapted to supply the different gases used in the deposition process and for cleaning. The improved susceptor consists of a standard carbon plate coated with a polysilicon film to protect it against said cleaning gases when they are aggressive to carbon. The present invention also encompasses a method of fabricating said improved susceptor.
    Type: Grant
    Filed: July 12, 2001
    Date of Patent: August 3, 2004
    Assignee: International Business Machines Corporation
    Inventors: Patrick Raffin, Fabrice Delarue, Jean Marc Waechter, Christophe Balsan, Joel Journe
  • Publication number: 20040137762
    Abstract: A device and method for annealing a wafer. The preferred embodiment includes applying a basic thermal budget to a weakened zone of a wafer, substantially evenly over the weakened zone. The basic thermal budget is insufficient to detach a detachment layer from a remainder of the wafer at the weakened zone. An additional thermal budget is applied locally in an initiation region of the weakened zone to initiate the detachment of the detachment layer at the weakened zone.
    Type: Application
    Filed: November 20, 2003
    Publication date: July 15, 2004
    Inventors: Walter Schwarzenbach, Jean-Marc Waechter
  • Publication number: 20020173164
    Abstract: There is disclosed a high throughput multideposition SACVD reactor that enables the rapid thermal deposition of dielectric materials such as Si3N4, SiO2, and SiON and non-dielectric materials such as polysilicon onto a semiconductor substrate in the same chamber according to the desired sequence. Such a reactor has a processing chamber which is well adapted to single semiconductor wafer processing. The processing chamber includes an improved susceptor to support the wafer and a specific gas distribution system adapted to supply the different gases used in the deposition process and for cleaning. The improved susceptor consists of a standard carbon plate coated with a polysilicon film to protect it against said cleaning gases when they are aggressive to carbon. The present invention also encompasses a method of fabricating said improved susceptor.
    Type: Application
    Filed: July 12, 2001
    Publication date: November 21, 2002
    Applicant: International Business Machines Corporation
    Inventors: Patrick Raffin, Fabrice Delarue, Jean Marc Waechter, Christophe Balsan, Joel Journe