Patents by Inventor Jean-Michel Riviere

Jean-Michel Riviere has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11935992
    Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.
    Type: Grant
    Filed: October 13, 2022
    Date of Patent: March 19, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11916353
    Abstract: Electronic device comprising a support substrate having a mounting face and an electronic chip having a rear face bonded on the mounting face by a volume of adhesive, wherein the support substrate comprises a plurality of wedging elements projecting from the mounting face so as to hold the chip bearing on contact areas of the wedging elements in a position substantially parallel to the mounting face of the support substrate.
    Type: Grant
    Filed: April 13, 2021
    Date of Patent: February 27, 2024
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Fabien Quercia, Jean-Michel Riviere
  • Patent number: 11908968
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Grant
    Filed: June 13, 2022
    Date of Patent: February 20, 2024
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11740416
    Abstract: An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.
    Type: Grant
    Filed: December 9, 2021
    Date of Patent: August 29, 2023
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Jean-Michel Riviere
  • Publication number: 20230245984
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Application
    Filed: March 29, 2023
    Publication date: August 3, 2023
    Applicants: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Denis FARISON, Romain COFFY, Jean-Michel RIVIERE
  • Patent number: 11641002
    Abstract: A device includes a substrate and an optoelectronic chip buried in the substrate. The substrate may include an opening above a first optical transduction region of the first optoelectronic chip and above a second optical transduction region of a second optoelectronic chip.
    Type: Grant
    Filed: March 11, 2021
    Date of Patent: May 2, 2023
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Alexandre Coullomb, Romain Coffy, Jean-Michel Riviere
  • Patent number: 11640946
    Abstract: A first integrated circuit chip is assembled to a second integrated circuit chip with a back-to-back surface relationship. The back surfaces of the integrated circuit chips are attached to each other using one or more of an adhesive, solder or molecular bonding. The back surface of at least one the integrated circuit chips is processed to include at least one of a trench, a cavity or a saw cut.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: May 2, 2023
    Assignees: STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Denis Farison, Romain Coffy, Jean-Michel Riviere
  • Publication number: 20230114469
    Abstract: A device includes comprising first and second printed circuit boards. Walls couple the first and second printed circuit boards to each other and define a first cavity between the first and second printed circuit boards. Electric conductors associated with the walls electrically connect the the first and second printed circuit boards. An integrated circuit chip is mounted to a first surface of the first integrated circuit board in the first cavity. The integrated circuit chip is electrically connected to conductive tracks of the first surface of the first printed circuit board. Surface-mounted components are mounted on top of and in contact with conductive tracks of a first surface of the second printed circuit board. The first surfaces of the first and second printed circuit boards are arranged facing towards each other. The first and second printed circuit boards may form rigid components of a flex-rigid type printed circuit board.
    Type: Application
    Filed: October 7, 2022
    Publication date: April 13, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Patrick LAURENT, Jean-Michel RIVIERE
  • Publication number: 20230034445
    Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.
    Type: Application
    Filed: October 13, 2022
    Publication date: February 2, 2023
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Patent number: 11546059
    Abstract: A cover for an electronic circuit package, including: a body having an opening extending therethrough; a first element located in the opening and having a surface continuing planar or rounded shapes of a surface of the cover; and a second element of connection of the first element to the body.
    Type: Grant
    Filed: February 5, 2021
    Date of Patent: January 3, 2023
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Jean-Michel Riviere, Romain Coffy, Karine Saxod
  • Patent number: 11527511
    Abstract: An electronic device includes a support substrate to which a first electronic chip and a second electronic chip are mounted in a position situated on top of one another. First electrical connection elements are interposed between the first electronic chip and the support substrate. Second electrical connection elements are interposed between the second electronic chip and the support substrate and are situated at a distance from a periphery of the first electronic chip. Third electrical connection elements are interposed between the first electronic chip and the second electronic chip.
    Type: Grant
    Filed: November 22, 2019
    Date of Patent: December 13, 2022
    Assignees: STMicroelectronics Pte Ltd, STMicroelectronics (Grenoble 2) SAS
    Inventors: David Gani, Jean-Michel Riviere
  • Patent number: 11502227
    Abstract: An electronic device includes a first electronic component and a second electronic. Each electronic component includes a carrier substrate having a back side and a front side, an electronic chip including an integrated optical element, an overmolded transparent block encapsulating the electronic chip above the carrier substrate, and electrical connections between the electronic chip and electrical contacts of the carrier substrate. An overmolded grid encapsulates and holds the first and second electronic components. The grid is configured so that sides of the first and second electronic components are at least partially exposed.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: November 15, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Publication number: 20220310869
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Application
    Filed: June 13, 2022
    Publication date: September 29, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Remi BRECHIGNAC, Jean-Michel RIVIERE
  • Patent number: 11437527
    Abstract: An encapsulation cover for an electronic package includes a frontal wall with a through-passage extending between faces. The frontal wall includes an optical element that allows light to pass through the through-passage. A cover body and a metal insert that is embedded in the cover body, with the cover body being overmolded over the metal insert, defines at least part of the frontal wall.
    Type: Grant
    Filed: June 9, 2020
    Date of Patent: September 6, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine Saxod, Veronique Ferre, Agnes Baffert, Jean-Michel Riviere
  • Patent number: 11387381
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated in a transparent block. An opaque conductive layer is applied to a top surface and a side surface of the transparent block. The receiver is mounted to the opaque conductive layer at the top surface. An electrical connection is made between the receiver and the opaque conductive layer. A conductive strip is also mounted to the side surface of the transparent block and isolated from the opaque conductive layer. A further electrical connection is made between the receiver and the conductive strip.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: July 12, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Patent number: 11380663
    Abstract: An opaque dielectric carrier and confinement substrate is formed by a stack of layers laminated on each other. The stack includes a solid back layer and a front frame having a peripheral wall and an intermediate partition which delimits two cavities located on top of the solid back layer and on either side of the intermediate partition. Electronic integrated circuit (IC) chips are located inside the cavities and mounted on top of the solid back layer. Each IC chip includes an integrated optical element. Electrical connections are provided between the IC chips and back electrical contacts of the solid back layer. Transparent encapsulation blocks are molded in the cavities to embed the IC chips.
    Type: Grant
    Filed: August 28, 2020
    Date of Patent: July 5, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Publication number: 20220196938
    Abstract: An optoelectronic element is located in a package. The package includes a first optical block and a second optical block that are attached to each other by a bonding layer. One of the first and second optical blocks is attached to lateral walls of the package by glue. The material of the bonding layer is configured to induce less stress to the first and second optical blocks than the glue.
    Type: Application
    Filed: December 9, 2021
    Publication date: June 23, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain COFFY, Jean-Michel RIVIERE
  • Patent number: 11322666
    Abstract: An optoelectronic device includes an emitter of light rays and a receiver of light rays. The emitter is encapsulated within a first encapsulation layer, and the receiver is encapsulated within a second encapsulation layer. An opaque layer covers the first encapsulation layer (encapsulating the receiver) and covers the second encapsulation layer (encapsulating the emitter). The first and second encapsulation layers are separated by a region of opaque material. This opaque material may be provided by the opaque layer or an opaque fill.
    Type: Grant
    Filed: October 15, 2020
    Date of Patent: May 3, 2022
    Assignee: STMicroelectronics (Grenoble 2) SAS
    Inventors: Romain Coffy, Remi Brechignac, Jean-Michel Riviere
  • Publication number: 20220029034
    Abstract: An encapsulation cover for an electronic package includes a frontal wall with a through-passage extending between faces. The frontal wall includes an optical element that allows light to pass through the through-passage. A cover body and a metal insert that is embedded in the cover body, with the cover body being overmolded over the metal insert, defines at least part of the frontal wall.
    Type: Application
    Filed: October 6, 2021
    Publication date: January 27, 2022
    Applicant: STMicroelectronics (Grenoble 2) SAS
    Inventors: Karine SAXOD, Veronique FERRE, Agnes BAFFERT, Jean-Michel RIVIERE
  • Patent number: 11211772
    Abstract: The disclosure concerns a housing for a light source mounted on a substrate, the housing comprising: a barrel comprising a mounting for a diffuser; and a diffuser positioned in the mounting, wherein the barrel comprises first and second conducting columns and a fuse or conductive wire electrically coupling the first and second conducting columns. A portion of the fuse is mechanically fixed to the diffuser and/or the fuse being arranged to trap the diffuser in said mounting.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: December 28, 2021
    Assignee: STMICROELECTRONICS (GRENOBLE 2) SAS
    Inventors: Romain Coffy, Jean-Michel Riviere