Abstract: A method for the dynamic reconfiguration of a signal frame structure, wherein each frame is structured in at least one subchannel having a number, order and/or format capable of being altered under the control of a reallocation command, time interleaving on N frames being selectively performed for each subchannel. According to the method, in the transient state, and for the N frames following a reallocation command, the procedure for writing data elements according to the interleaving law remains unchanged, in accordance with the new structure defined by a reallocation command, and a specific logic for rereading the memory plane is implemented so that the frames consist of uniform capacity units comprising data elements from the same source signal. The corresponding transmitters, receivers and signals are also disclosed.

Abstract: A frequency control device comprises, in the form of a phase-locked loop, a phase comparator, a filter, an oscillator producing a local clock signal and two divide-by-M frequency dividers. The dividers receive the local clock signal whose frequency is slaved to N times the frequency of a master clock signal, with M<N, and are looped to the inputs of the comparator. A first of the dividers is reinitialized at the frequency of the master clock signal. A load circuit loads the most-significant-bit stages of a counter included in the first divider with a binary word added to binary elements stored in most-significant-bit stages of a counter included in the second divider, after a resetting of the second divider following a general initialization of the device.

Abstract: A process for regenerating a periodic signal creates two signals. The first ignal provides for the detection of a periodic signal for a short time preceding the theoretical timing position of the periodic signal. The second signal is transmitted a very short time after the theoretical timing position of the periodic signal and serves as a substitute periodic signal, when the periodic signal has not been detected prior to a transmission of the second signal. The circuit, used to receive broadcasted digital data, is comprised of a counter (L), a D flip-flop (B1) and a clock (CLX) having a frequency which is equal to a multiple of the data bit rate which is to be received. The counter (L) has an initializing input connected to the Q output of the flip-flop (B1). It has two outputs (X, Y) corresponding to the transmissions of the first and second signals.

Abstract: This test equipment permits a testing of the demodulator of a teletex television receiver. It consists of a digital test signal generator, the output of which is connected to the HF input of the television, and a receiver, the input of which is connected to the video output of said receiver. The generator tramsmits pseudo-random data packets having a first frequency of binary elements, with two double-intervaled binary elements at two predetermined instants t.sub.1 and t.sub.2 for each packet. The receiver has a data regeneration circuit whose threshold varies line by line from a maximum value to a minimum value. The sampling clock of the receiver is at a second frequency lower than the first by the ratio (n-2)/n, where n is equal to the integral ratio of the first frequency to the line frequency of the television. A suitable means insures resynchronization of the sampling clock at the middle of each line.