Patents by Inventor Jed H. Rankin

Jed H. Rankin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190227427
    Abstract: An extreme ultraviolet (EUV) mask including an absorber structure is disclosed. The absorber structure may include at least one slanted and/or concave sidewall. The absorber structure may include a sidewall including a step. A method of forming an absorber for an EUV mask is disclosed. The method may include etching an absorber layer using a mask to form an absorber structure having a sidewall wherein an outer edge of the top surface of the sidewall is closer to a central vertical axis of the absorber structure than an outer edge of the bottom surface of the sidewall. The method may include performing additional etching steps to form a step along the sidewall of the absorber structure. The etching may include combinations of anisotropic etching in different directions, and/or isotropic etching. The method may include etching an absorber layer including multiple absorber layers having different material properties on the ML reflector.
    Type: Application
    Filed: January 22, 2018
    Publication date: July 25, 2019
    Inventors: Amr Y. Abdo, Lei Zhuang, Jed H. Rankin
  • Publication number: 20190219933
    Abstract: Embodiments of a method include: converting at least one image of a printed mask to a plurality of representative contours, each corresponding to mask patterns in the printed mask; determining whether the printed mask includes a printing defect based on whether the plurality of representative contours violates a set of contour tolerances for the printed mask; in response to at least one of plurality of representative contours violating at least one of the set of contour tolerances: identifying a location where a representative contour violates the at least one of the set of contour tolerances, and generating an instruction to adjust a layout for the printed mask, based on the violating of the at least one of the set of contour tolerances; and in response to none of the plurality of representative contours violating the set of contour tolerances, flagging a layout for the printed mask as compliant.
    Type: Application
    Filed: January 18, 2018
    Publication date: July 18, 2019
    Inventors: Liang Cao, Jed H. Rankin, Jie Zhang, Yulu Chen
  • Publication number: 20190121022
    Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.
    Type: Application
    Filed: December 11, 2018
    Publication date: April 25, 2019
    Inventors: John J. ELLIS-MONAGHAN, Jeffrey P. GAMBINO, Mark D. JAFFE, Kirk D. PETERSON, Jed H. RANKIN
  • Publication number: 20190080038
    Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to mask structures and methods of manufacture. The method includes determining a plane through a frontside surface and a backside surface of a mask, each plane representing a flatness of the frontside surface and the backside surface, respectively; subtracting, using at least one computing device, a difference between the plane of the frontside surface and the plane of the backside surface to find a thickness variation; generating, using the at least one computing device, a fitting to fit the thickness variation; and subtracting, using the at least one computing device, the fitting from the thickness variation to generate a residual structure for collecting a residual flatness measurement.
    Type: Application
    Filed: January 11, 2018
    Publication date: March 14, 2019
    Inventors: Christina TURLEY, Jed H. RANKIN, Xuemei CHEN, Allen H. GABOR, Timothy A. BRUNNER
  • Patent number: 10191213
    Abstract: Methods and structures for shielding optical waveguides are provided. A method includes forming a first optical waveguide core and forming a second optical waveguide core adjacent to the first optical waveguide core. The method also includes forming an insulator layer over the first optical waveguide core and the second optical waveguide core. The method further includes forming a shielding structure in the insulator layer between the first optical waveguide core and the second optical waveguide core.
    Type: Grant
    Filed: January 9, 2014
    Date of Patent: January 29, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • Patent number: 10008597
    Abstract: A method includes forming a hardmask over one or more gate structures. The method further includes forming a photoresist over the hardmask. The method further includes forming an opening in the photoresist over at least one of the gate structures. The method further includes stripping the hardmask that is exposed in the opening and which is over the at least one of the gate structures. The method further includes removing the photoresist. The method further includes providing a halo implant on a side of the least one of the at least one of the gate structures.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: June 26, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Darshana N. Bhagat, Thomas J. Dunbar, Yen L. Lim, Jed H. Rankin, Eva S. Holmes
  • Patent number: 9946152
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to modified surfaces of extreme ultraviolet lithography photomasks and methods of manufacture. The structure includes a reflective surface having a patterned design, and a black border region at edges of the patterned design. The black border region includes a modified surface morphology to direct light away from reaching a subsequent mirror.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: April 17, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhengqing John Qi, Christina A. Turley, Jed H. Rankin
  • Patent number: 9927698
    Abstract: A method and system for: forming a first rectangular shape with photomask writing equipment, using a first sub-threshold dosage on a photoresist layer of a photomask substrate; forming an overlapping second rectangular shape with the photomask writing equipment using a second sub-threshold dosage on the photoresist layer, the second rectangular shape being rotated relative to the first rectangular shape to form one of: a hexagonal overlap area and an octagonal overlap area, that exposes the photoresist layer to at least a threshold dosage; and forming a photomask, based on developing the exposed photoresist layer, to provide optical transmission corresponding to the one of: the hexagonal overlap area of at least the threshold dosage and the octagonal overlap area of at least the threshold dosage, for use by a photolithography system to write any of a contact, a via, or a curvilinear shape on an integrated circuit substrate.
    Type: Grant
    Filed: August 11, 2016
    Date of Patent: March 27, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jed H. Rankin, Adam C. Smith
  • Publication number: 20180046073
    Abstract: A method and system for: forming a first rectangular shape with photomask writing equipment, using a first sub-threshold dosage on a photoresist layer of a photomask substrate; forming an overlapping second rectangular shape with the photomask writing equipment using a second sub-threshold dosage on the photoresist layer, the second rectangular shape being rotated relative to the first rectangular shape to form one of: a hexagonal overlap area and an octagonal overlap area, that exposes the photoresist layer to at least a threshold dosage; and forming a photomask, based on developing the exposed photoresist layer, to provide optical transmission corresponding to the one of: the hexagonal overlap area of at least the threshold dosage and the octagonal overlap area of at least the threshold dosage, for use by a photolithography system to write any of a contact, a via, or a curvilinear shape on an integrated circuit substrate.
    Type: Application
    Filed: August 11, 2016
    Publication date: February 15, 2018
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: JED H. RANKIN, ADAM C. SMITH
  • Publication number: 20170315438
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to modified surfaces of extreme ultraviolet lithography photomasks and methods of manufacture. The structure includes a reflective surface having a patterned design, and a black border region at edges of the patterned design. The black border region includes a modified surface morphology to direct light away from reaching a subsequent mirror.
    Type: Application
    Filed: April 27, 2016
    Publication date: November 2, 2017
    Inventors: Zhengqing John Qi, Christina A. Turley, Jed H. Rankin
  • Patent number: 9791771
    Abstract: Disclosed are a repairable photomask structure and extreme ultraviolet (EUV) photolithography methods. The structure includes a multilayer stack, a protective layer above the stack and a light absorber layer above the protective layer. The stack includes alternating layers of high and low atomic number materials and a selected one of the high atomic number material layers is different from the others such that it functions as an etch stop layer. This configuration allows the photomask structure to be repaired if/when defects are detected near exposed surfaces of the multilayer stack following light absorber layer patterning. For example, when a defect is detected near an exposed surface of the stack in a specific opening in the light absorber layer, the opening can be selectively extended down to the etch stop layer or all the openings can be extended down to the etch stop layer in order to remove that defect.
    Type: Grant
    Filed: February 11, 2016
    Date of Patent: October 17, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Zhengqing John Qi, Jed H. Rankin
  • Patent number: 9740080
    Abstract: Various particular embodiments include an optical structure, including: a photonic microring including an integral signal detector for detecting a level of an optical signal in the photonic microring; and a controller, coupled to the signal detector, for selectively adjusting a resonant frequency of the photonic microring based on the detected level of the optical signal in the photonic microring.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: August 22, 2017
    Assignee: International Business Machines Corporation
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • Publication number: 20170235217
    Abstract: Disclosed are a repairable photomask structure and extreme ultraviolet (EUV) photolithography methods. The structure includes a multilayer stack, a protective layer above the stack and a light absorber layer above the protective layer. The stack includes alternating layers of high and low atomic number materials and a selected one of the high atomic number material layers is different from the others such that it functions as an etch stop layer. This configuration allows the photomask structure to be repaired if/when defects are detected near exposed surfaces of the multilayer stack following light absorber layer patterning. For example, when a defect is detected near an exposed surface of the stack in a specific opening in the light absorber layer, the opening can be selectively extended down to the etch stop layer or all the openings can be extended down to the etch stop layer in order to remove that defect.
    Type: Application
    Filed: February 11, 2016
    Publication date: August 17, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: Zhengqing John Qi, Jed H. Rankin
  • Publication number: 20170123290
    Abstract: Various particular embodiments include an optical structure, including: a photonic microring including an integral signal detector for detecting a level of an optical signal in the photonic microring; and a controller, coupled to the signal detector, for selectively adjusting a resonant frequency of the photonic microring based on the detected level of the optical signal in the photonic microring.
    Type: Application
    Filed: October 30, 2015
    Publication date: May 4, 2017
    Inventors: John J. Ellis-Monaghan, Jeffrey P. Gambino, Mark D. Jaffe, Kirk D. Peterson, Jed H. Rankin
  • Publication number: 20170069518
    Abstract: An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: Brett Cucci, Thai Doan, Jeffrey P. Gambino, Rebecca K. Kelley, Jed H. Rankin, Daniel S. Vanslette
  • Patent number: 9508578
    Abstract: An apparatus and method for leak detection of coolant gas from a chuck. The apparatus includes a chuck having a top surface and configured to clamp a substrate to the top surface, the chuck having one or more recessed regions in the top surface, the recessed regions configured to allow a cooling gas to contact a backside of the substrate; a cooling gas inlet and a cooling gas outlet connected to the one or more recessed regions; a first measurement device connected to the cooling gas inlet and configured to measure a first amount of cooling gas entering the cooling gas inlet and a second measurement device connected to the cooling gas outlet and configured to measure a second amount of cooling gas exiting from the cooling gas outlet; and a controller configured to determine a difference between the first amount of cooling gas and the second amount of cooling gas.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: November 29, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Shawn A. Adderly, Samantha D. DiStefano, Jeffrey P. Gambino, Max G. Levy, Max L. Lifson, Jed H. Rankin, Timothy D. Sullivan
  • Patent number: 9437595
    Abstract: A structure includes at least one shallow trench isolation structure formed in a substrate to isolate adjacent different type devices. The structure further includes a barrier trench structure formed in the substrate to isolate diffusions of adjacent same type devices. The structure further includes a material spanning the barrier trench structure to connect the diffusions of the adjacent same type device, on a same level as the adjacent same type devices.
    Type: Grant
    Filed: April 15, 2015
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Brent A. Anderson, Andres Bryant, Edward J. Nowak, Jed H. Rankin
  • Patent number: 9436789
    Abstract: A structure, method and system for complementary strain fill for integrated circuit chips. The structure includes a first region of an integrated circuit having multiplicity of n-channel and p-channel field effect transistors (FETs); a first stressed layer over n-channel field effect transistors (NFETs) of the first region, the first stressed layer of a first stress type; a second stressed layer over p-channel field effect transistors (PFETs) of the first region, the second stressed layer of a second stress type, the second stress type opposite from the first stress type; and a second region of the integrated circuit, the second region not containing FETs, the second region containing first sub-regions of the first stressed layer and second sub-regions of the second stressed layer.
    Type: Grant
    Filed: October 17, 2014
    Date of Patent: September 6, 2016
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Brent A. Anderson, Edward J. Nowak, Jed H. Rankin
  • Patent number: 9276002
    Abstract: The present disclosure generally provides for an integrated circuit (IC) structure with a bulk silicon finFET and methods of forming the same. An IC structure according to the present disclosure can include: a bulk substrate; a finFET located on a first region of the bulk substrate; and a layered dummy structure located on a second region of the bulk substrate, wherein the layered dummy structure includes a first crystalline semiconductive layer, a second crystalline semiconductive layer positioned on the first crystalline semiconductive layer, wherein the first crystalline semiconductive layer comprises a material distinct from the second crystalline semiconductive layer, and a third crystalline semiconductive layer positioned on the second crystalline semiconductive layer, wherein the third crystalline semiconductive layer comprises the material distinct from the second crystalline semiconductive layer.
    Type: Grant
    Filed: June 9, 2015
    Date of Patent: March 1, 2016
    Assignee: GlobalFoundries, Inc.
    Inventors: Kangguo Cheng, Ali Khakifirooz, Qizhi Liu, Edward J. Nowak, Jed H. Rankin
  • Patent number: 9263517
    Abstract: Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: February 16, 2016
    Assignee: GLOBALFOUNDRIES. INC.
    Inventors: Wagdi W. Abadeer, Kiran V. Chatty, Jason E. Cummings, Toshiharu Furukawa, Robert J. Gauthier, Jed H. Rankin, Robert R. Robison, William R. Tonti