Patents by Inventor Jeff C. Morriss
Jeff C. Morriss has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240020259Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: July 14, 2023Publication date: January 18, 2024Applicant: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Publication number: 20230073807Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: July 8, 2022Publication date: March 9, 2023Applicant: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 11386033Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: December 14, 2020Date of Patent: July 12, 2022Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 11113225Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: June 5, 2020Date of Patent: September 7, 2021Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 11108433Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.Type: GrantFiled: November 30, 2018Date of Patent: August 31, 2021Assignee: Intel CorporationInventors: Henning Braunisch, Georgios Dogiamis, Jeff C. Morriss, Hyung-Jin Lee, Richard Dischler, Ajay Balankutty, Telesphor Kamgaing, Said Rami
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Publication number: 20210097015Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: December 14, 2020Publication date: April 1, 2021Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Publication number: 20200409896Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: June 5, 2020Publication date: December 31, 2020Applicant: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 10784204Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.Type: GrantFiled: July 2, 2016Date of Patent: September 22, 2020Assignee: Intel CorporationInventors: Kemal Aygun, Richard J. Dischler, Jeff C. Morriss, Zhiguo Qian, Wilfred Gomes, Yu Amos Zhang, Ram S. Viswanath, Rajasekaran Swaminathan, Sriram Srinivasan, Yidnekachew S. Mekonnen, Sanka Ganesan, Eduard Roytman, Mathew J. Manusharow
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Patent number: 10678736Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: GrantFiled: September 25, 2015Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Publication number: 20200066641Abstract: Integrated circuit (IC) chip die to die channel interconnect configurations (systems and methods for their manufacture) may improve signaling to and through a single ended bus data signal communication channel by including on-die induction structures; on-die interconnect features; on-package first level die bump designs and ground webbing structures; on-package high speed horizontal data signal transmission lines; on-package vertical data signal transmission interconnects; and/or on-package electro-optical (EO) connectors in various die to die interconnect configurations for improved signal connections and transmission through a data signal channel extending through one or more semiconductor device package devices, that may include an electro-optical (EO) connector upon which at least one package device may be mounted, and/or be semiconductor device packages in a package-on-package configuration.Type: ApplicationFiled: July 2, 2016Publication date: February 27, 2020Inventors: Kemal AYGUN, Richard J. DISCHLER, Jeff C. MORRISS, Zhiguo QIAN, Wilfred GOMES, Yu Amos ZHANG, Ram S. VISWANATH, Rajasekaran SWAMINATHAN, Sriram SRINIVASAN, Yidnekachew S. MEKONNEN, Sanka GANESAN, Eduard ROYTMAN, Mathew J. MANUSHAROW
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Patent number: 10396036Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).Type: GrantFiled: December 26, 2015Date of Patent: August 27, 2019Assignee: Intel CorporationInventors: Yu Amos Zhang, Zhiguo Qian, Kemal Aygun, Yidnekachew S. Mekonnen, Gregorio R. Murtagian, Sanka Ganesan, Eduard Roytman, Jeff C. Morriss
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Publication number: 20190115951Abstract: Embodiments herein may relate to an interconnect that includes a transceiver, wherein the transceiver is configured to generate a single side band (SSB) signal for communication over a waveguide and a waveguide interconnect to communicate the SSB signal over the waveguide. In an example, an SSB operator is configured to generate the SSB signal and the SSB signal can be generated by use of a finite-impulse response filter. Other embodiments may be described and/or claimed.Type: ApplicationFiled: November 30, 2018Publication date: April 18, 2019Applicant: Intel CorporationInventors: Henning Braunisch, Georgios Dogiamis, Jeff C. Morriss, Hyung-Jin Lee, Richard Dischler, Ajay Balankutty, Telesphor Kamgaing, Said Rami
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Publication number: 20180331043Abstract: A vertically ground isolated package device can include (1) ground shielding attachment structures and shadow voiding for data signal contacts; (2) vertical ground shielding structures and shield fencing of vertical data signal interconnects; and (3) ground shielding for an electro-optical module connector of the package device. These reduce cross talk between data signal contacts, attachment structures and vertical “signal” interconnects of the package device. The ground shielding attachment structures may include patterns of solder bumps and/or surface contacts. The shadow voiding may be surrounding voids in ground planes that are larger than the data signal solder bumps. The vertical ground shielding structures may include patterns of ground shield interconnects between the vertical data signal interconnects: The shield fencing may include patterns of ground plated through holes (PTH) and micro-vias (uVia).Type: ApplicationFiled: December 26, 2015Publication date: November 15, 2018Inventors: Yu Amos ZHANG, Zhiguo QIAN, Kemal AYGUN, Yidnekachew S. MEKONNEN, Gregorio R. MURTAGIAN, Sanka GANESAN, Eduard ROYTMAN, Jeff C. MORRISS
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Publication number: 20180276164Abstract: An interconnect interface is provided to enable communication with an off-package device over a link including a plurality of lanes. Logic of the interconnect interface includes receiver logic to receive a valid signal from the off-package device on a dedicated valid lane of the link indicating that data is to arrive on a plurality of dedicated data lanes in the plurality of lanes, receive the data on the data lanes from the off-package device sampled based on arrival of the valid signal, and receive a stream signal from the off-package device on a dedicated stream lane in the plurality of lanes. The stream signal corresponds to the data and indicates a particular data type of the data. The particular data type can be one of a plurality of different data types capable of being received on the plurality of data lanes of the link.Type: ApplicationFiled: September 25, 2015Publication date: September 27, 2018Inventors: Debendra Das Sharma, Zuoguo Wu, Mahesh Wagh, Mohiuddin M. Mazumder, Venkatraman Iyer, Jeff C. Morriss
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Patent number: 9524265Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.Type: GrantFiled: December 3, 2014Date of Patent: December 20, 2016Assignee: Intel CorporationInventors: David J. Harriman, Jeff C. Morriss
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Publication number: 20150089107Abstract: In one embodiment, the present invention includes a host controller with transmit logic to prepare data into a packet for communication along an interconnect and to transmit the packet. This packet may include a preamble portion having a first predetermined value, a content portion including the data and having a plurality of symbols each including a start bit separate from the data, an error detection portion including an inverted version of the content portion, and a postamble portion having a second predetermined value. Other embodiments are described and claimed.Type: ApplicationFiled: December 3, 2014Publication date: March 26, 2015Inventors: David J. Harriman, Jeff C. Morriss
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Publication number: 20090171163Abstract: Apparatus and method provide for forming a modular medical device by selecting a combination of medical device modules and combining them to form the modular medical device, for example by plugging them together or into a common bus. In one embodiment, the modules are selected from a group of modules adapted to be used in combination to perform one or more medical functions for a particular patient. In one embodiment at least one module is adapted to store data, at least one module is adapted to perform a communication function, at least one module is used to control the medical device, at least one module is adapted to provide a sense function, and at least one module provides energy to the medical device. In another embodiment the modular medical devices may be rented or sold to patients, or prescribed by physicians and covered by medical insurance.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: John W. Mates, Jeff C. Morriss
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Publication number: 20080252348Abstract: In some embodiments, an apparatus includes a printed circuit board substrate, a copper signal line disposed on the printed circuit board substrate, and a nonlinear transmission structure coupled to the copper signal line, wherein the nonlinear transmission structure is configured to sharpen a wavefront of a high speed signal pulse on the copper signal line. In some embodiments, the nonlinear transmission structure may include a voltage dependent dielectric layer on the printed circuit board substrate. In some embodiments, the voltage dependent dielectric layer may include a plurality of varactors positioned at a receiving end of the signal line.Type: ApplicationFiled: December 28, 2006Publication date: October 16, 2008Inventors: Eric C. Hannah, Jeff C. Morriss
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Patent number: 7315599Abstract: A skew correction circuit includes a first circuit and a second circuit. The first circuit generates at least one pulse train signal in response to a data bit signal and a first strobe signal. A duty cycle of the pulse train signal is indicative of a degree of skew between the data bit signal and the strobe signal. The second circuit is coupled to the first circuit to produce a second strobe signal and regulate a timing relationship between the data bit signal and the second strobe signal based on the duty cycle of the pulse train.Type: GrantFiled: December 29, 1999Date of Patent: January 1, 2008Assignee: Intel CorporationInventor: Jeff C. Morriss
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Patent number: 5623610Abstract: Circuitry and complementary logic are provided to a bus controller, a number of 1:n bus signal distributors, and a number of bus interfaces of an hierarchical serial bus assembly for the bus controller to dynamically detect and manage the interconnection topology of the serial bus elements. The serial bus assembly is used to serially interface a number of isochronous and asynchronous peripherals to the system unit of a computer system. These circuitry and complementary logic support an hierarchical view of the serial bus elements, logically dividing the hierarchy into multiple tiers. This logical view of the serial bus elements is used by the bus controller to detect the presence of interconnected serial bus elements and the functions of the bus agents, i.e.Type: GrantFiled: October 31, 1994Date of Patent: April 22, 1997Assignee: Intel CorporationInventors: Shaun Knoll, Jeff C. Morriss, Shelagh Callahan, Ajay V. Bhatt, Sudarshan B. Cadambi