Patents by Inventor Jeff Jiao

Jeff Jiao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100201703
    Abstract: Systems and methods for improving throughput of a graphics processing unit are disclosed. In one embodiment, a system includes a multithreaded execution unit capable of processing requests to access a constant cache, a vertex attribute cache, at least one common register file, and an execution unit data path substantially simultaneously.
    Type: Application
    Filed: April 21, 2010
    Publication date: August 12, 2010
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Yang (Jeff) JIAO
  • Publication number: 20100123717
    Abstract: Among several systems and methods related to graphics processing as described herein, an embodiment of a graphics processing unit (GPU), which comprises a unified shader device and control device, is disclosed. The unified shader device of the GPU is configured to perform multiple graphics shading functions and includes a plurality of execution units. The execution units are configured to operate in parallel, where each execution unit itself has a plurality of threads also configured to operate in parallel. Each thread is configured to perform multiple graphics shading functions. The control device of the GPU, which is in communication with the shader device, is configured to receive graphics data and allocate portions of the graphics data to at least one thread of at least one execution unit. The control device is adapted to dynamically reallocate the graphics data from threads that are determined to be busy to threads that are determined to be less busy.
    Type: Application
    Filed: November 20, 2008
    Publication date: May 20, 2010
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Yang (Jeff) Jiao
  • Publication number: 20090251476
    Abstract: Embodiments of systems and methods for managing a constant buffer with rendering context specific data in multithreaded parallel computational GPU core are disclosed. Briefly described, one method embodiment, among others, comprises responsive to a first shader operation, receiving at a constant buffer a first group of constants corresponding to a first rendering context, and responsive to a second shader operation, receiving at the constant buffer a second group of constants corresponding to a second context without flushing the first group.
    Type: Application
    Filed: April 4, 2008
    Publication date: October 8, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Yang (Jeff) Jiao, Yijung SU, John Brothers
  • Publication number: 20090189909
    Abstract: Graphics processing units (GPUs) are used, for example, to process data related to three-dimensional objects or scenes and to render the three-dimensional data onto a two-dimensional display screen. One embodiment, among others, of a unified cache system used in a GPU comprises a data storage device and a storage device controller. The data storage device is configured to store graphics data processed by or to be processed by one or more shader units. The storage device controller is placed in communication with the data storage device. The storage device controller is configured to dynamically control a storage allocation of the graphics data within the data storage device.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Jeff Jiao, Timour Paltashev
  • Publication number: 20090189896
    Abstract: Graphics processing units (GPUs) are used, for example, to process data related to three-dimensional objects or scenes and to render the three-dimensional data onto a two-dimensional display screen. One embodiment, among others, of a GPU is disclosed herein, wherein the GPU includes a control device configured to receive vertex, geometry and pixel data. The GPU further includes a plurality of execution units connected in parallel, each execution unit configured to perform a plurality of graphics shading functions on the vertex, geometry and pixel data. The control device is further configured to allocate a portion of the vertex, geometry and pixel data to each execution unit in a manner to substantially balance the load among the execution units.
    Type: Application
    Filed: January 25, 2008
    Publication date: July 30, 2009
    Applicant: VIA Technologies, Inc.
    Inventors: Jeff Jiao, Timour Paltashev
  • Publication number: 20090182948
    Abstract: Systems and methods for sharing a physical cache among one or more clients in a stream data processing pipeline are described. One embodiment, among others, is directed to a system for sharing caches between two or more clients. The system comprises a physical cache memory having a memory portion accessed through a cache index. The system further comprises at least two virtual cache spaces mapping to the memory portion and at least one virtual cache controller configured to perform a hit-miss test on the active window of the virtual cache space in response to a request from one of the clients for accessing the physical cache memory. In accordance with some embodiments, each of the virtual cache spaces has an active window which has a different size than the memory portion. Furthermore, data is accessed from the corresponding location of the memory portion when the hit-miss test of the cache index returns a hit.
    Type: Application
    Filed: January 16, 2008
    Publication date: July 16, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Jeff Jiao, Timour Paltashev
  • Publication number: 20090153570
    Abstract: A system for integrating triangle setup and attribute setup operations into a programmable execution unit of a graphics processing unit is disclosed. A method for integrating triangle setup and attribute setup operations into a programmable execution unit graphics processing unit is also disclosed. In one embodiment, at least one execution unit is configured for multi-threaded operation. The at least one execution unit is configured to execute at least one thread for triangle setup operations and attribute setup operations as well as threads for pixel shader, geometry shader and vertex shader operations.
    Type: Application
    Filed: December 12, 2007
    Publication date: June 18, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Yang (Jeff) Jiao, Mike Hong, Yin Li, Yunjie Xu
  • Publication number: 20090147017
    Abstract: Various embodiments of shader processing systems and methods are disclosed. One method embodiment, among others, comprises a dependent texture read method executed using a multi-threaded, parallel computational core of a graphics processing unit (GPU). Such a method includes generating a dependent texture read request at logic configured to perform shader computations corresponding to a first thread, and sending shader-calculated, texture-sampling related parameters corresponding to the first thread to a texture pipeline while retaining at the logic all other shader processing related information corresponding to the first thread.
    Type: Application
    Filed: December 6, 2007
    Publication date: June 11, 2009
    Applicant: VIA TECHNOLOGIES, INC.
    Inventor: Yang (Jeff) Jiao
  • Patent number: 7454599
    Abstract: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.
    Type: Grant
    Filed: September 19, 2005
    Date of Patent: November 18, 2008
    Assignee: Via Technologies, Inc.
    Inventors: Yang (Jeff) Jiao, Yiping Chen, Wen-Chung Chen
  • Publication number: 20080282034
    Abstract: A method and a computing system are provided. The computing system may include a system memory configured to store data in a first data format. The computing system may also include a computational core comprising a plurality of execution units (EU). The computational core may be configured to request data from the system memory and to process data in a second data format. Each of the plurality of EU may include an execution control and datapath and a specialized L1 cache pool. The computing system may include a multipurpose L2 cache in communication with the each of the plurality of EU and the system memory. The multipurpose L2 cache may be configured to store data in the first data format and the second data format. The computing system may also include an orthogonal data converter in communication with at least one of the plurality of EU and the system memory.
    Type: Application
    Filed: July 18, 2008
    Publication date: November 13, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Yang (Jeff) Jiao, Yiping Chen, Timour Paltashev
  • Publication number: 20080192063
    Abstract: Provided is a system for managing multiple contexts in a decentralized graphics processing unit. The system includes multiple control units that can include a context buffer, a context processor, and a context scheduler. Also included is logic to receive multiple contexts, logic to identify at least one of the contexts, and logic to facilitate communication among the control units.
    Type: Application
    Filed: February 8, 2007
    Publication date: August 14, 2008
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Qunfeng (Fred) Liao, Yang (Jeff) Jiao, Yijung Su
  • Patent number: 7286139
    Abstract: A method for rendering a visible portion of an image that includes a plurality of graphics primitives. The size of the graphics primitives may be large and require the use of floating point numbers to represent the vertices. When the graphics primitives have a common vertex that is visible, the edge functions for the primitive are computed so as to avoid the common vertex becoming different for the different primitives. If the other vertices of the graphics primitives lie outside a bounding rectangle, then a vertex is formed at the intersection of the bounding rectangle and the graphics primitive. Fixed point numbers for the common vertex and other vertices including intersection vertices are then used to compute edge functions of the primitive and the primitive is rendered using the edge functions. If the common vertex is not visible, then floating point numbers are used to compute the edge functions.
    Type: Grant
    Filed: September 17, 2004
    Date of Patent: October 23, 2007
    Assignee: Via Technologies, Inc.
    Inventor: Yang (Jeff) Jiao
  • Publication number: 20070182746
    Abstract: The present disclosure describes implementations for processing instructions and data across multiple Arithmetic Logic Units (ALUs). In one implementation, a graphics processing apparatus comprises a plurality of ALUs configured to process independent instructions in parallel. Pre-processing logic is configured to receive instructions and associated data to be directed to one of the plurality of ALUs for processing from a register file, the pre-processing logic being configured to selectively format received instructions for delivery to a plurality of the ALUs. In addition, post-processing logic is configured to receive data output from the plurality of the ALUs and deliver the received data to the register file for write-back, the post-processing logic being configured to selectively format data output from a plurality of the ALUs for delivery to the register file as though the data had been output by a single ALU.
    Type: Application
    Filed: December 13, 2006
    Publication date: August 9, 2007
    Applicant: VIA TECHNOLOGIES, INC.
    Inventors: Yang (Jeff) Jiao, Chien Te Ho
  • Publication number: 20070091088
    Abstract: The present disclosure is directed to novel methods and apparatus for managing or performing the dynamic allocation or reallocation of processing resources among a vertex shader, a geometry shader, and pixel shader of a graphics processing unit. Specifically, embodiments of the invention embody or comprise plurality of execution units, wherein each execution unit is configured for multi-threaded operation. Logic is provided for receiving requests from each of a plurality of shader stages to perform shader-related computations, and scheduling threads within the plurality of execution units to perform the requested shader-related computations. The threads within the execution units of the pool are individually scheduled to perform shader-related computations, such that a given thread can be scheduled over time to perform shader operations for different shader stages.
    Type: Application
    Filed: April 19, 2006
    Publication date: April 26, 2007
    Inventors: Yang (Jeff) Jiao, Yijung Su
  • Publication number: 20070067607
    Abstract: The present disclosure provides for processing units, which are capable of concurrently executing instructions, and a source arbitrator. The source arbitrator determines whether instructions for the processing units are read from different sources. If the source arbitrator determines that each processing unit reads its respective instruction from a different source, then the instructions from the various sources are provided to their corresponding processing units for substantially concurrent processing.
    Type: Application
    Filed: September 19, 2005
    Publication date: March 22, 2007
    Inventors: Yang (Jeff) Jiao, Yiping Chen, Wen-Chung Chen
  • Patent number: 7164430
    Abstract: A system and method for rendering a non-zero thickness line on a pixel-limited output device such that aliasing of the line is reduced. The edges defining a line segment are expanded to insure that any pixel touched by the line segment has its center included in the bounds of the line segment. The area of any pixel partially or fully covered by the expanded line is determined. If one edge of the line traverses the pixel, the area is determined according to whether a triangular or triangular plus parallelogram area is covered. If more than one edge of the line segment traverses a pixel, the area covered is computed based on the single edge case. With the area covered by the line segment known, the color or shading of the pixel is determined by linear interpolation between the line and the background.
    Type: Grant
    Filed: September 25, 2003
    Date of Patent: January 16, 2007
    Assignee: VIA Technologies, Inc.
    Inventors: Yang (Jeff) Jiao, Zhou (Mike) Hong
  • Patent number: 7088359
    Abstract: A method and apparatus for reordering the vertices of a graphics primitive. The vertices of the primitive are received in a circular order, but the position of the vertices in the circular order is arbitrary. The vertices include coordinates with respect to an origin. Comparison logic operates on the coordinates of each vertex to determine which vertex is the minimum vertex, which the vertex that is a minimum distance away from the origin. Once the minimum vertex is known, the vertices are shuffled into the proper order, with the minimum vertex in the lowest order position, the next vertex in circular order in the next position and so on. An apparatus saves the information for reordering the vertices, so that the order is preserved for parameter information for each vertex.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: August 8, 2006
    Assignee: VIA Technologies, Inc.
    Inventors: Hsilin Huang, Jeff Jiao, Chiente Ho
  • Publication number: 20040212611
    Abstract: A method and apparatus for reordering the vertices of a graphics primitive. The vertices of the primitive are received in a circular order, but the position of the vertices in the circular order is arbitrary. The vertices include coordinates with respect to an origin. Comparison logic operates on the coordinates of each vertex to determine which vertex is the minimum vertex, which the vertex that is a minimum distance away from the origin. Once the minimum vertex is known, the vertices are shuffled into the proper order, with the minimum vertex in the lowest order position, the next vertex in circular order in the next position and so on. An apparatus saves the information for reordering the vertices, so that the order is preserved for parameter information for each vertex.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 28, 2004
    Inventors: Hsilin Huang, Jeff Jiao, Chiente Ho