Patents by Inventor Jeffery Robinson Childress

Jeffery Robinson Childress has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10157656
    Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 18, 2018
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9780143
    Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: October 3, 2017
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9673387
    Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.
    Type: Grant
    Filed: December 5, 2016
    Date of Patent: June 6, 2017
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Publication number: 20170084827
    Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.
    Type: Application
    Filed: December 5, 2016
    Publication date: March 23, 2017
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Publication number: 20170062034
    Abstract: A magnetic memory cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. Steering of current is provided for programming the magnetic memory cell.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 2, 2017
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Publication number: 20170062519
    Abstract: A magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits and a method for implementing magnetic memory integrated with complementary metal oxide semiconductor (CMOS) driving circuits for use in Solid-State Drives (SSDs) are provided. A complementary metal oxide semiconductor (CMOS) wafer is provided, and a magnetic memory is formed on top of the CMOS wafer providing a functioning magnetic memory chip.
    Type: Application
    Filed: August 25, 2015
    Publication date: March 2, 2017
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9520444
    Abstract: A magnetic memory pillar cell and a method for implementing the magnetic memory cell for use in Solid-State Drives (SSDs) are provided. A magnetic memory cell includes a first conductor M1, and a second conductor M2, the second conductor M1 surrounded by the first conductor M1 and a programmable area using unpatterned programmable magnetic media. At least one of the conductors M1, M2 is formed of a magnetic material, and the conductor M2 is more conductive than conductor M1. An oxide barrier extends between the first conductor M1 and a programmable input to the magnetic memory pillar cell; and the oxide barrier is unpatterned.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: December 13, 2016
    Assignee: Western Digital Technologies, Inc.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson
  • Patent number: 9443905
    Abstract: A three-dimensional (3D) scalable magnetic memory array and a method for implementing the three-dimensional (3D) scalable magnetic memory array for use in Solid-State Drives (SSDs) are provided. A three-dimensional (3D) scalable magnetic memory array includes an interlayer dielectric (IDL) stack of word planes separated by a respective IDL. A plurality of pillar holes is formed in the IDL stack in a single etch step; each of the pillar holes including an oxide barrier coating, and a first conductor M1, and a second conductor M2 forming magnetic pillar memory cells. The first conductor M1 is formed of a magnetic material, and the second conductor M2 is more electrically conductive than the conductor M1; and each of the magnetic pillar memory cell inside the pillar holes have a programmable area using unpatterned programmable magnetic media proximate to a respective one of the word planes.
    Type: Grant
    Filed: August 25, 2015
    Date of Patent: September 13, 2016
    Assignee: HGST Netherlands B.V.
    Inventors: Zvonimir Z. Bandic, Jeffery Robinson Childress, Luiz M. Franca-Neto, Jordan Asher Katine, Neil Leslie Robertson