Patents by Inventor Jeffrey A. Levin

Jeffrey A. Levin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9647921
    Abstract: Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: May 9, 2017
    Assignee: QUALCOMM Incorporated
    Inventors: Venkat Rangan, Jeffrey A. Levin, Rodolfo G. Beraha
  • Patent number: 9418331
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for creating tags (static or dynamic) for input/output classes of a neural network model using supervised learning. The method includes augmenting a neural network model with a plurality of neurons and training the augmented network using spike timing dependent plasticity (STDP) to determine one or more tags.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: August 16, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Vikram Gupta, Regan Blythe Towal, Victor Hokkiu Chan, Ravindra Manohar Patwardhan, Jeffrey Levin
  • Patent number: 9373074
    Abstract: Certain aspects of the present disclosure provide techniques for time management and scheduling of synchronous neural processing on a cluster of processing nodes. A slip (or offset) may be introduced between processing nodes of a distributed processing system formed by a plurality of interconnected processing nodes, to enable faster nodes to continue processing without waiting for slower nodes to catch up. In certain aspects, a processing node, after completing each processing step, may check for received completion packets and apply a defined constraint to determine whether it may start processing a subsequent step or not.
    Type: Grant
    Filed: October 9, 2012
    Date of Patent: June 21, 2016
    Assignee: QUALCOMM Incorporated
    Inventors: Jeffrey A. Levin, Venkat Rangan, Robert J. Vachon
  • Patent number: 9224089
    Abstract: Certain aspects of the present disclosure support a technique for adaptive bit-allocation in neural systems. Bit-allocation for neural signals and parameters in a neural network described in the present disclosure may comprise for a plurality of synapse circuits in the neural simulator network, dynamically allocating a number of bits to the neural circuit signals based on at least one characteristic of one or more neural potential in the neural simulator network; and for the plurality of synapse circuits in the neural simulator network, dynamically allocating a number of bits to at least one neural processing parameter of the synapse circuit based on at least one condition of the neural simulator network.
    Type: Grant
    Filed: August 7, 2012
    Date of Patent: December 29, 2015
    Assignee: QUALCOMM Incorporated
    Inventors: Somdeb Majumdar, Venkat Rangan, Jeffrey A. Levin
  • Publication number: 20150120626
    Abstract: Certain aspects of the present disclosure provide methods and apparatus for creating tags (static or dynamic) for input/output classes of a neural network model using supervised learning. The method includes augmenting a neural network model with a plurality of neurons and training the augmented network using spike timing dependent plasticity (STDP) to determine one or more tags.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Applicant: QUALCOMM Incorporated
    Inventors: Vikram GUPTA, Regan Blythe TOWAL, Victor Hokkiu CHAN, Ravindra Manohar Patwardhan, Jeffrey LEVIN
  • Patent number: 8909575
    Abstract: Certain aspects of the present disclosure support a method of designing the resource model in hardware (or software) for learning spiking neural networks. The present disclosure comprises accounting for resources in a different domain (e.g., negative log lack-of-resources instead of availability of resources), modulating weight changes for multiple spike events upon a single trigger, and strategically advancing or retarding the resource replenishment or decay (respectively) to overcome the limitation of single event-based triggering.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: December 9, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Jason Frank Hunzinger, Jeffrey A. Levin
  • Patent number: 8892485
    Abstract: Certain embodiments of the present disclosure support implementation of a neural processor with synaptic weights, wherein training of the synapse weights is based on encouraging a specific output neuron to generate a spike. The implemented neural processor can be applied for classification of images and other patterns.
    Type: Grant
    Filed: July 8, 2010
    Date of Patent: November 18, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Vladimir Aparin, Jeffrey A. Levin
  • Patent number: 8838896
    Abstract: The present patent application discloses a method and apparatus for using external and internal memory for cancelling traffic interference comprising storing data in an external memory; and processing the data samples on an internal memory, wherein the external memory is low bandwidth memory; and the internal memory is high bandwidth on board cache. The present method and apparatus also comprises caching portions of the data on the internal memory, filling the internal memory by reading the newest data from the external memory and updating the internal memory; and writing the older data back to the external memory from the internal memory, wherein the data is incoming data samples.
    Type: Grant
    Filed: May 20, 2008
    Date of Patent: September 16, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Senthil Govindaswamy, Jeffrey A. Levin, Raghu Sagar Madala, Sharad Deepak Sambhwani
  • Publication number: 20140101661
    Abstract: Certain aspects of the present disclosure provide techniques for time management and scheduling of synchronous neural processing on a cluster of processing nodes. A slip (or offset) may be introduced between processing nodes of a distributed processing system formed by a plurality of interconnected processing nodes, to enable faster nodes to continue processing without waiting for slower nodes to catch up. In certain aspects, a processing node, after completing each processing step, may check for received completion packets and apply a defined constraint to determine whether it may start processing a subsequent step or not.
    Type: Application
    Filed: October 9, 2012
    Publication date: April 10, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Jeffrey A. Levin, Venkat Rangan, Robert J. Vachon
  • Patent number: 8694452
    Abstract: Certain embodiments of the present disclosure support techniques for power efficient implementation of neuron synapses with positive and/or negative synaptic weights.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: April 8, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Vladimir Aparin, Jeffrey A. Levin
  • Publication number: 20140043962
    Abstract: Certain aspects of the present disclosure support techniques for collecting system information in a network on a chip (NoC). A dedicated packet may be transmitted from a source node to a destination node. As it traverses through the NoC, the dedicated packet may collect information from various nodes, which may be made available by the destination node. The collected information may be used in an effort to detect failures and collect statistics regarding the NoC.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Venkat Rangan, Jeffrey A. Levin, Rodolfo G. Beraha
  • Publication number: 20140046885
    Abstract: Certain aspects of the present disclosure support a technique for optimized representation of variables in neural systems. Bit-allocation for neural signals and parameters in a neural network described in the present disclosure may comprise allocating quantization levels to the neural signals based on at least one measure of sensitivity of a pre-determined performance metric to quantization errors in the neural signals, and allocating bits to the parameters based on the at least one measure of sensitivity of the pre-determined performance metric to quantization errors in the parameters.
    Type: Application
    Filed: August 7, 2012
    Publication date: February 13, 2014
    Applicant: QUALCOMM Incorporated
    Inventors: Somdeb Majumdar, Venkat Rangan, Jeffrey A. Levin
  • Patent number: 8644264
    Abstract: Methods and systems for estimating and canceling pilot interference in a wireless (e.g., CDMA) communication system. In one method, a received signal comprised of a number of signal instances, each including a pilot, is initially processed to provide data samples. Each signal instance's pilot interference may be estimated by despreading the data samples with a spreading sequence for the signal instance, channelizing the despread data to provide pilot symbols, filtering the pilot symbols to estimate the channel response of the signal instance, and multiplying the estimated channel response with the spreading sequence. The pilot interference estimates due to a plurality of interfering multipaths are accumulated to derive the total pilot interference, which is subtracted from the data samples to provide pilot-canceled data samples. These samples are then processed to derive demodulated data for each of at least one (desired) signal instance in the received signal.
    Type: Grant
    Filed: October 7, 2010
    Date of Patent: February 4, 2014
    Assignee: Qualcomm Incorporated
    Inventors: Alessandro Vanelli Coralli, Henry David Pfister, Jilei Hou, John Edward Smee, Roberto Padovani, Brian K. Butler, Jeffrey A. Levin, Thomas B. Wilborn, Paul E. Bender
  • Patent number: 8625337
    Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.
    Type: Grant
    Filed: May 5, 2011
    Date of Patent: January 7, 2014
    Assignee: QUALCOMM Incorporated
    Inventors: Wenqing Wu, Kendrick H. Yuen, Xiaochun Zhu, Seung H. Kang, Matthew Michael Nowak, Jeffrey A. Levin, Robert Gilmore, Nicholas Yu
  • Patent number: 8611311
    Abstract: Methods and systems for estimating and canceling pilot interference in a wireless (e.g., CDMA) communication system. In one method, a received signal comprised of a number of signal instances, each including a pilot, is initially processed to provide data samples. Each signal instance's pilot interference may be estimated by despreading the data samples with a spreading sequence for the signal instance, channelizing the despread data to provide pilot symbols, filtering the pilot symbols to estimate the channel response of the signal instance, and multiplying the estimated channel response with the spreading sequence. The pilot interference estimates due to a plurality of interfering multipaths are accumulated to derive the total pilot interference, which is subtracted from the data samples to provide pilot-canceled data samples. These samples are then processed to derive demodulated data for each of at least one (desired) signal instance in the received signal.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: December 17, 2013
    Assignee: Qualcomm Incorporated
    Inventors: Alessandro Vanelli Coralli, Henry David Pfister, Jilei Hou, John Edward Smee, Roberto Padovani, Brian K Butler, Jeffrey A Levin, Thomas B Wilborn, Paul E Bender
  • Patent number: 8606732
    Abstract: Certain embodiments of the present disclosure support techniques for simplified hardware implementation of the reward-modulated spike-timing-dependent plasticity (STDP) learning rule in networks of spiking neurons.
    Type: Grant
    Filed: August 4, 2010
    Date of Patent: December 10, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Subramaniam Venkatraman, Venkat Rangan, Jeffrey A. Levin
  • Publication number: 20130226851
    Abstract: Certain aspects of the present disclosure support a method of designing the resource model in hardware (or software) for learning spiking neural networks. The present disclosure comprises accounting for resources in a different domain (e.g., negative log lack-of-resources instead of availability of resources), modulating weight changes for multiple spike events upon a single trigger, and strategically advancing or retarding the resource replenishment or decay (respectively) to overcome the limitation of single event-based triggering.
    Type: Application
    Filed: February 29, 2012
    Publication date: August 29, 2013
    Applicant: QUALCOMM Incorporated
    Inventors: Jason Frank Hunzinger, Jeffrey A. Levin
  • Patent number: 8433665
    Abstract: The present disclosure proposes implementation of a three-memristor synapse where an adjustment of synaptic strength is based on Spike-Timing-Dependent Plasticity (STDP) with dopamine signaling.
    Type: Grant
    Filed: July 7, 2010
    Date of Patent: April 30, 2013
    Assignee: QUALCOMM Incorporated
    Inventors: Yi Tang, Jeffrey A. Levin, Vladimir Aparin, Venkat Rangan
  • Publication number: 20120036099
    Abstract: Certain embodiments of the present disclosure support techniques for simplified hardware implementation of the reward-modulated spike-timing-dependent plasticity (STDP) learning rule in networks of spiking neurons.
    Type: Application
    Filed: August 4, 2010
    Publication date: February 9, 2012
    Applicant: QUALCOMM INCORPORATED
    Inventors: Subramaniam Venkatraman, Venkat Rangan, Jeffrey A. Levin
  • Publication number: 20120011091
    Abstract: Certain embodiments of the present disclosure support techniques for power efficient implementation of neuron synapses with positive and/or negative synaptic weights.
    Type: Application
    Filed: July 7, 2010
    Publication date: January 12, 2012
    Applicant: QUALCOMM Incorporated
    Inventors: Vladimir Aparin, Jeffrey A. Levin